Alternate physical layer power mode

Abstract

A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

What is claimed is: 
     
         1 . An apparatus comprising:
 physical layer (PHY) circuitry comprising a physical coding sublayer, wherein the PHY circuitry is configured to alternatively support at least two different power control settings;   a PHY Interface for the PCI Express (PIPE)-based interface to couple the PHY circuitry to a media access control (MAC) layer, wherein the interface comprises a set of data pins, a set of command pins, a set of status pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings,   wherein the PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.   
     
     
         2 . The apparatus of  claim 1 , wherein the indication comprises values permanently set at the plurality of power control pins, and the values comprise a code to identify the particular power control setting. 
     
     
         3 . The apparatus of  claim 1 , wherein the indication comprises at least one signal sent from the MAC layer on the plurality of power control pins, and the signal specifies a binary value comprising two or more bits to identify the particular power control setting. 
     
     
         4 . The apparatus of  claim 1 , wherein the at least two power control settings comprise a standard power control setting and an alternative power control setting. 
     
     
         5 . The apparatus of  claim 4 , wherein the alternative power control setting comprises a power control setting associated with channels with short physical lengths. 
     
     
         6 . The apparatus of  claim 4 , wherein the at least two power control settings comprise a plurality of alternative power control settings. 
     
     
         7 . The apparatus of  claim 4 , wherein the alternative power control setting corresponds to implementation of the physical layer in a multi-chip package. 
     
     
         8 . The apparatus of  claim 4 , wherein alternating current (AC) coupling is to be used in the standard power control setting and direct current (DC) coupling is to be used in the alternative power control setting. 
     
     
         9 . The apparatus of  claim 1 , further comprising a PHY integrated circuit (IC) device comprising the PHY circuitry and the interface, wherein the PHY IC device is discrete from the MAC layer. 
     
     
         10 . The apparatus of  claim 1 , further comprising a microcell comprising the PHY circuitry and the interface. 
     
     
         11 . The apparatus of  claim 1 , wherein the parameters comprise one or more of a transmitter swing parameter, a receiver equalization parameter, a clock recovery parameter, and a link training state machine parameter. 
     
     
         12 . An apparatus comprising:
 a media access control (MAC) layer block comprising:
 state machine logic to implement a link training and status state machine of a particular interconnect protocol; and 
 circuitry to generate signals according to the particular interconnect protocol; and 
   a PHY Interface for the PCI Express (PIPE)-based interface to couple to a physical layer device to implement at least a physical coding sublayer of a physical layer, wherein the interface comprises a set of data pins, a set of command pins, a set of status pins, and a plurality of power control pins to indicate a particular one of at least two power control settings to be implemented on the physical layer device,   wherein the circuitry is further to generate a value at the power control pins to indicate the particular power control setting to the physical layer device and the particular power control setting comprises settings for a short-reach link.   
     
     
         13 . The apparatus of  claim 12 , wherein the particular interconnect protocol comprises one of a protocol based on PCIe, USB, SATA, Display Port, or Converged IO. 
     
     
         14 . The apparatus of  claim 12 , further comprising a power setting detector to determine that the particular power control setting is to be applied and cause the particular power control setting to be indicated at the power control pins of the interface. 
     
     
         15 . The apparatus of  claim 12 , further comprising a multi-chip package comprising the MAC layer block and the physical layer device, wherein the physical layer device is to interconnect at least a portion of devices in the multi-chip package using the short-reach link, and the particular power control setting is to be indicated based on inclusion of the physical layer device in the multi-chip package. 
     
     
         16 . A system comprising:
 media access control (MAC) circuitry; and   physical layer (PHY) circuitry discrete from the MAC, comprising a physical coding sublayer, wherein the PHY circuitry is configured to alternatively support at least two different power control settings,   wherein the MAC circuitry couples with the PHY circuitry through a defined interface comprising a set of data pins, a set of command pins, a set of status pins, and a plurality of power control pins, wherein the plurality of power control pins are to indicate a particular one of the at least two power control settings to be implemented on by the PHY circuitry.   
     
     
         17 . The system of  claim 16 , further comprising a multi-chip package device comprising the MAC circuitry and the PHY circuitry, wherein the PHY circuitry is to provide an interconnect for devices internal to the multi-chip package device. 
     
     
         18 . The system of  claim 17 , wherein the PHY circuitry is to further provide a port to connect to devices external to the multi-chip package device over a link. 
     
     
         19 . The system of  claim 18 , wherein the PHY circuitry is to implement a physical layer of the link according to a particular interconnect protocol. 
     
     
         20 . The system of  claim 16 , wherein the interface comprises a PHY Interface for the PCI Express (PIPE)-based interface.