US2020006489A1PendingUtilityA1

MOSFET Having Drain Region Formed Between Two Gate Electrodes with Body Contact Region and Source Region Formed in a Double Well Region

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Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Jul 3, 2012Filed: Sep 12, 2019Published: Jan 2, 2020
Est. expiryJul 3, 2032(~6 yrs left)· nominal 20-yr term from priority
H10W 10/031H10W 10/30H01L 29/0623H01L 29/0696H01L 29/0852H01L 29/1083H01L 29/7835H01L 29/0653H01L 29/0638H01L 27/088H01L 27/092H01L 29/7816H01L 29/7833H01L 21/761H01L 29/1095H01L 29/66659H10D 84/85H10D 84/83H10D 62/393H10D 62/152H10D 62/127H10D 62/116H10D 62/112H10D 62/107H10D 30/603H10D 30/601H10D 30/0221H10D 30/65H10D 62/371
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Claims

Abstract

A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A transistor structure comprising:
 a drain region in a first side of a gate region;   a body contact and a source region in a second side of the gate region, wherein the body contact and the source region are placed in an alternating manner from a top view; and   a stacked well region comprising:
 a first region of a first conductivity formed over a substrate of the first conductivity; and 
 a second region of the first conductivity, wherein the second region is embedded in the first region. 
   
     
     
         2 . The transistor structure of  claim 1 , wherein:
 the source region and the body contact are in the second region of the stacked well region.   
     
     
         3 . The transistor structure of  claim 1 , further comprising:
 a lightly doped source region adjacent to the source region in the second region of the stacked well region.   
     
     
         4 . The transistor structure of  claim 1 , further comprising:
 a lightly doped drain region adjacent to the drain region in the first region of the substrate.   
     
     
         5 . The transistor structure of  claim 1 , wherein:
 the second region of the stacked well region has a higher doping density than the first region of the stacked well region.   
     
     
         6 . The transistor structure of  claim 1 , further comprising a second gate region adjacent to the drain region, the second gate region being different from the gate region. 
     
     
         7 . The transistor structure of  claim 6 , further comprising a second stacked well region adjacent to the second gate region, the second stacked well region comprising a third region of the first conductivity formed over the substrate, the third region is embedded in the first region. 
     
     
         8 . The transistor structure of  claim 1 , further comprising a body pickup ring surrounding the source region. 
     
     
         9 . The transistor structure of  claim 8 , wherein the body pickup ring has the first conductivity. 
     
     
         10 . The transistor structure of  claim 1 , wherein a ration of the source region to the body contact is in a range from 10:1 to about 2:1. 
     
     
         11 . A device comprising:
 a substrate of a first conductivity;   a gate electrode over the substrate;   a first drain/source region and a second drain/source region disposed on opposite sides of the gate electrode in the substrate, wherein the first drain/source region and the second drain/source region have a second conductivity;   a first doped well having the first conductivity formed under the first drain/source region;   a second doped well having the first conductivity formed under the first drain/source region, wherein the first doped well is embedded in the second doped well, and wherein the first doped well and the second doped well are configured such that a doping density gradually declines from the first drain/source region to the second drain/source region; and   a body contact region of the first conductivity formed adjacent to the first drain/source region in the substrate, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.   
     
     
         12 . The device of  claim 11 , further comprising:
 a body pickup ring of the first conductivity surrounding the first drain/source region.   
     
     
         13 . The device of  claim 11 , further comprising:
 a first lightly doped drain/source region formed adjacent to the first drain/source region in at least one doped well.   
     
     
         14 . The device of  claim 11 , further comprising:
 a first lightly doped drain/source region and a second lightly doped drain/source region symmetrical relative to the gate electrode, and adjacent to the first drain/source region and the second drain/source region respectively.   
     
     
         15 . The device of  claim 11 , wherein a ratio of the first drain/source region to the body contact region is in a range from 10:1 to about 2:1. 
     
     
         16 . A transistor comprising:
 a first transistor comprising a first gate, a first source, a first drain and a first body contact, wherein:
 the first body contact and the first source are formed in an alternating manner from a top view; and 
 the first source formed in a first stacked well region, wherein the first stacked well region comprises:
 a first region of a first conductivity formed over a substrate of the first conductivity; and 
 a second region of the first conductivity embedded in the first region; 
 
   a second transistor comprising a second gate, a second source, a second drain and a second body contact, wherein the first drain and the second drain are coupled together, and wherein:
 the second body contact and the second source are formed in an alternating manner from a top view; 
 the second source formed in a second stacked well region, wherein the first stacked well region comprises:
 a third region of the first conductivity formed over the substrate; and 
 a fourth region of the first conductivity embedded in the third region; and 
 
   a body pickup ring surrounding the first transistor and the second transistor.   
     
     
         17 . The transistor of  claim 16 , further comprising:
 a body pickup ring of the first conductivity surrounding the first transistor and the second transistor in the substrate.   
     
     
         18 . The transistor of  claim 16 , further comprising:
 a first lightly doped source/drain region with the first conductivity adjacent to the first source in the second region.   
     
     
         19 . The transistor of  claim 16 , further comprising:
 a second lightly doped drain/source region with the first conductivity formed adjacent to the first drain in the substrate, wherein the second lightly doped drain/source region is under the first gate.   
     
     
         20 . The transistor of  claim 16 , wherein:
 the second region has a higher doping density than the first region.

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