Fully self-aligned via

Abstract

A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

What is claimed is: 
     
         1 . An electronic device comprising:
 a first metallization layer comprising a set of first conductive lines extending along a first direction on a first insulating layer on a substrate;   a second insulating layer on the first insulating layer;   a second metallization layer comprising a set of second conductive lines on the second insulating layer and a third insulating layer above the first metallization layer, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and   a via between the first metallization layer and the second metallization layer, wherein the via is self-aligned along the second direction to one of the first conductive lines.   
     
     
         2 . The electronic device of  claim 1 , wherein the via is self-aligned along the first direction to one of the second conductive lines. 
     
     
         3 . The electronic device of  claim 1 , wherein the third insulating layer is etch selective relative to the second insulating layer. 
     
     
         4 . The electronic device of  claim 1 , further comprising a liner on the first conductive lines. 
     
     
         5 . The electronic device of  claim 1 , wherein the via has a trench portion that is a part of the one of the second conductive lines and a via portion underneath the trench portion. 
     
     
         6 . The electronic device of  claim 1 , wherein the third insulating layer is deposited on the first conductive lines. 
     
     
         7 . The electronic device of  claim 1 , wherein the via is formed in the second insulating layer. 
     
     
         8 . A method to provide a self-aligned via, comprising:
 recessing first conductive lines on a first insulating layer on a substrate, the first   
       conductive lines extending along a first direction on the first insulating layer;
 forming pillars on the recessed first conductive lines; 
 depositing a second insulating layer between the pillars; 
 removing the pillars to form trenches in the second insulating layer; 
 depositing a third insulating layer through the trenches onto the recessed first conductive lines; and 
 etching the third insulating layer selectively relative to the second insulating layer to form a via opening down to one of the first conductive lines. 
 
     
     
         9 . The method of  claim 8 , wherein the via opening is self-aligned along the first direction and a second direction to the one of the first conductive lines, the second direction crossing the first direction at an angle. 
     
     
         10 . The method of  claim 8 , further comprising selectively growing a seed layer on the recessed first conductive lines, wherein the pillars are formed on the seed layer. 
     
     
         11 . The method of  claim 8 , further comprising forming a hard mask layer on at least one of the second insulating layer and the third insulating layer. 
     
     
         12 . The method of  claim 8 , further comprising depositing a liner on the recessed first conductive lines. 
     
     
         13 . The method of  claim 8 , further comprising depositing a conductive layer into the via opening. 
     
     
         14 . The method of  claim 8 , wherein the via opening has a trench portion and a via portion underneath the trench portion. 
     
     
         15 . A system to manufacture an electronic device, comprising:
 a processing chamber comprising a pedestal to hold an electronic device structure comprising a first metallization layer comprising a set of first conductive lines extending along a first direction on a first insulating layer on a substrate;   a plasma source coupled to the processing chamber to generate plasma; and   a processor coupled to the plasma source, the processor having a first configuration to control recessing the first conductive lines, the processor having a second configuration to control forming pillars on the recessed first conductive lines, the processor having a third configuration to control depositing a second insulating layer between the pillars: the processor having a fourth configuration to control removing the pillars to form trenches in the second insulating layer, the processor having a fifth configuration to control depositing a third insulating layer through the trenches onto the recessed first conductive lines; and the processor having a sixth configuration to control etching the third insulating layer selectively relative to the second insulating layer to form a via opening down to one of the first conductive lines.   
     
     
         16 . The system of  claim 15 , wherein the via opening is self-aligned along the first direction and a second direction, the second direction crossing the first direction at an angle. 
     
     
         17 . The system of  claim 15 , wherein the processor has a sixth configuration to control selectively growing a seed layer on the recessed first conductive lines, wherein the pillars are formed on the seed layer. 
     
     
         18 . The system of  claim 15 , wherein the processor has a seventh configuration to control forming a hard mask layer on at least one of the second insulating layer and the third insulating layer. 
     
     
         19 . The system of  claim 15 , wherein the processor has an eight configuration to control depositing a liner on the recessed first conductive lines. 
     
     
         20 . The system of  claim 15 , wherein the processor has a ninth configuration to control depositing a conductive layer into the via opening.