Methods, apparatus, and system for reducing leakage current in semiconductor devices

Abstract

Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

1 .- 7 . (canceled) 
     
     
         8 . A semiconductor device, comprising:
 a semiconductor substrate;   a well region comprising a first impurity and disposed in the semiconductor substrate;   a gate on the semiconductor substrate above the well region;   two doped S/D regions comprising at least one third impurity and disposed in the semiconductor substrate, one on each side of the gate; and   two depletion regions, one below and essentially not disposed on sides of each doped S/D region, each depletion region comprising at least one second impurity at a concentration below the concentration of the at least one third impurity in the doped S/D regions, wherein the first impurity is of a first type and the at least one second impurity and the at least one third impurity are of a second type opposite the first type.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first impurity is a p-type impurity and the at least one second impurity and the at least one third impurity are n-type impurities. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the first impurity is an n-type impurity and the at least one second impurity and the at least one third impurity are p-type impurities. 
     
     
         11 . The semiconductor device of  claim 8 , wherein each depletion region has a crescent cross section. 
     
     
         12 . The semiconductor device of  claim 8 , wherein each depletion region has a rectangular cross section. 
     
     
         13 .- 19 . (canceled) 
     
     
         20 . The semiconductor device of  claim 8 , wherein each depletion region and each doped S/D region are disposed in the well region. 
     
     
         21 . The semiconductor device of  claim 8 , wherein each doped S/D region is an epitaxial doped S/D region. 
     
     
         22 . A semiconductor device, comprising:
 a semiconductor substrate;   a gate on the semiconductor substrate;   two doped S/D regions comprising at least one first impurity and disposed in the semiconductor substrate, one on each side of the gate; and   two depletion regions, one below and essentially not disposed on sides of each doped S/D region, each depletion region comprising at least one second impurity at a concentration below the concentration of the at least one first impurity in the doped S/D regions, wherein the at least one first impurity and the at least one second impurity are of a first type.   
     
     
         23 . The semiconductor device of  claim 22 , wherein the at least one first impurity and the at least one second impurity are n-type impurities. 
     
     
         24 . The semiconductor device of  claim 22 , wherein the at least one first impurity and the at least one second impurity are p-type impurities. 
     
     
         25 . The semiconductor device of  claim 22 , wherein each depletion region has a crescent cross section. 
     
     
         26 . The semiconductor device of  claim 22 , wherein each depletion region has a rectangular cross section. 
     
     
         27 . A semiconductor device, comprising:
 a semiconductor substrate;   a well region comprising a first impurity and disposed in the semiconductor substrate;   a gate on the semiconductor substrate above the well region;   two doped S/D regions comprising at least one third impurity and disposed in the semiconductor substrate, one on each side of the gate, wherein a top of each doped S/D region is above a top of the well region; and   two depletion regions, one below and essentially not disposed on sides of each doped S/D region, each depletion region comprising at least one second impurity at a concentration below the concentration of the at least one third impurity in the doped S/D regions, wherein the first impurity is of a first type and the at least one second impurity and the at least one third impurity are of a second type opposite the first type.   
     
     
         28 . The semiconductor device of  claim 27 , wherein the first impurity is a p-type impurity and the at least one second impurity and the at least one third impurity are n-type impurities. 
     
     
         29 . The semiconductor device of  claim 27 , wherein the first impurity is an n-type impurity and the at least one second impurity and the at least one third impurity are p-type impurities. 
     
     
         30 . The semiconductor device of  claim 27 , wherein each depletion region has a crescent cross section. 
     
     
         31 . The semiconductor device of  claim 27 , wherein each depletion region has a rectangular cross section. 
     
     
         32 . The semiconductor device of  claim 27 , wherein each depletion region and each doped S/D region are disposed in the well region. 
     
     
         33 . The semiconductor device of  claim 27 , wherein each doped S/D region is an epitaxial doped S/D region.