Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate

Abstract

A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10 17 atoms/cm 3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

1 . A method for producing a three-dimensional structure, comprising:
 processing a surface layer of a silicon substrate to form a three-dimensional shape, the surface layer having an oxygen concentration of 1×10 17  atoms/cm 3  or more; and   performing a heat treatment to form an oxide film on a surface of the three-dimensional shape to produce the three-dimensional structure.   
     
     
         2 . The method for producing the three-dimensional structure according to  claim 1 , wherein the surface layer has an oxygen concentration of 1×10 18  atoms/cm 3  or more. 
     
     
         3 . The method for producing the three-dimensional structure according to  claim 1 , wherein the three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in a thickness direction of the silicon substrate is between 1 nm and 1000 nm. 
     
     
         4 . The method for producing the three-dimensional structure according to  claim 3 , wherein the height of the three-dimensional structure is between 1 nm and 100 nm. 
     
     
         5 . The method for producing the three-dimensional structure according to  claim 3 , wherein the three-dimensional structure has a length of between 1 nm and 10000 nm in a direction vertical to the thickness direction of the silicon substrate and has a width of between 1 nm and 100 nm in a direction vertical to the thickness direction of the silicon substrate. 
     
     
         6 . The method for producing the three-dimensional structure according to  claim 1 , wherein the three-dimensional shape is formed by processing the surface layer by etching. 
     
     
         7 . The method for producing the three-dimensional structure according to  claim 1 , wherein the silicon substrate is a monocrystalline silicon substrate. 
     
     
         8 . A method for producing a vertical transistor, comprising:
 producing transistors using a three-dimensional structure having the oxide film produced according to the method for producing the three-dimensional structure according to  claim 1 .   
     
     
         9 . A vertical transistor wafer comprising a silicon substrate having a surface layer having an oxygen concentration of 1×10 17  atoms/cm 3  or more. 
     
     
         10 . The vertical transistor wafer according to  claim 9 , wherein the surface layer has an oxygen concentration of 1×10 18  atoms/cm 3  or more. 
     
     
         11 . A vertical transistor substrate comprising:
 a silicon substrate; and   a three-dimensional structure provided on a surface layer of the silicon substrate, wherein   the three-dimensional structure has a core mainly consisting of Si and being continuous from the silicon substrate and a film formed from SiO 2  and covering a surface of the core, and a height difference of projections and recesses having a period of 10 nm or smaller on an interface between the film and the core is 1.5 nm or smaller.   
     
     
         12 . A three-dimensional structure transistor including a three-dimensional structure of which the diameter or the shortest side is 1 μm or smaller, wherein the transistor is fabricated using a three-dimensional structure obtained by processing an Si substrate in which at least an oxygen concentration in a region up to a depth in a height direction of the three-dimensional structure is 1×10 18  atoms/cm 3  or more.