Semiconductor device and method for manufacturing the same

Abstract

A semiconductor package according to an embodiment includes a semiconductor chip having a first surface in which a chip pad is formed, a first insulating layer arranged on the first surface of the semiconductor chip and including a first filler, a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer, a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer, a second insulating layer contacting the redistribution pattern on the first insulating layer and including a second filler, a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer, an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer, and an external connection terminal electrically connected to the UBM.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a semiconductor chip having a first surface in which a chip pad is formed;   a first insulating layer arranged on the first surface of the semiconductor chip and comprising a first filler;   a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer; and   a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising:
 a second insulating layer contacting the redistribution pattern on the first insulating layer and comprising a second filler;   a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer;   an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer; and   an external connection terminal electrically connected to the UBM.   
     
     
         3 . The semiconductor package of  claim 2 , wherein the first filler and the second filler comprise at least one of silica and alumina, and have a size of from about 0.1 micrometers to about 10 micrometers. 
     
     
         4 . The semiconductor package of  claim 2 , wherein the first conductive via has a tapered shape, and has a diameter of from 5 micrometers to 20 micrometers. 
     
     
         5 . The semiconductor package of  claim 2 , wherein the first insulating layer has a thickness of from 10 micrometers to 100 micrometers,
 wherein the second insulating layer has a thickness of from 10 micrometers to 100 micrometers.   
     
     
         6 . The semiconductor package of  claim 2 , wherein the redistribution pattern has a thickness of from 1 micrometer to 5 micrometers. 
     
     
         7 . The semiconductor package of  claim 2 , wherein a mixing proportion of the first filler of the first insulating layer is different from a mixing proportion of the second filler of the second insulating layer. 
     
     
         8 . The semiconductor package of  claim 7 , wherein the mixing proportion of the first filler of the first insulating layer is lower than the mixing proportion of the second filler of the second insulating layer. 
     
     
         9 . The semiconductor package of  claim 2 , wherein the first insulating layer comprises:
 a first upper adhesive layer on the semiconductor chip; and   a first filler layer arranged on the first upper adhesive layer and comprising the first filler, and   wherein the second insulating layer comprises:   a second upper adhesive layer on the first filler layer; and   
       a second filler layer arranged on the second upper adhesive layer and comprising the second filler. 
     
     
         10 . The semiconductor package of  claim 9 , wherein the first insulating layer further comprises a first lower adhesive layer between the first filler layer and the second upper adhesive layer, and
 wherein the second insulating layer further comprises a second lower adhesive layer on the second filler layer.   
     
     
         11 . The semiconductor package of  claim 1 , wherein the first filler has a high density in a region of the first insulating layer adjacent to the first conductive via and the redistribution pattern. 
     
     
         12 . The semiconductor package of  claim 1 , wherein the redistribution pattern is tapered so that a cross-sectional area thereof decreases in a direction towards the semiconductor chip. 
     
     
         13 . The semiconductor package of  claim 1 , wherein a sum of thicknesses of the first conductive via and the redistribution pattern is the same as a thickness of the first insulating layer. 
     
     
         14 . The semiconductor package of  claim 1 , wherein a lower surface of the redistribution pattern is closer to the semiconductor chip in a vertical direction than an upper surface of the first insulating layer. 
     
     
         15 . A semiconductor package comprising:
 a semiconductor chip having a first surface in which a chip pad is formed;   a first insulating layer on the first surface of the semiconductor chip;   a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer;   a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer;   a second insulating layer contacting the redistribution pattern on the first insulating layer;   a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer;   an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer; and   an external connection terminal electrically connected to the UBM,   wherein the redistribution pattern   is tapered so that a cross-sectional area thereof decreases in a direction towards the semiconductor chip.   
     
     
         16 . The semiconductor package of  claim 15 , wherein a cross-section of the redistribution pattern has a shape of at least one of a triangle, a trapezoid, a stair, and a semicircle. 
     
     
         17 . The semiconductor package of  claim 15 , wherein the first insulating layer comprises a first filler, and the second insulating layer comprises a second filler. 
     
     
         18 . A method of manufacturing a semiconductor package, the method comprising:
 forming a first insulating layer on a first surface of a semiconductor chip in which a chip pad is formed, the first insulating layer comprising a first filler;   forming a first via hole and a redistribution pattern hole by stamping the first insulating layer;   forming a first conductive via and a redistribution pattern by filling the first via hole and the redistribution pattern hole with a first conductive material;   forming a second insulating layer on the first insulating layer, the second insulating layer comprising a second filler;   forming a second via hole and an under bump material (UBM) pattern hole by stamping the second insulating layer; and   forming a second conductive via and a UBM by filling the second via hole and the UBM pattern hole with a second conductive material.   
     
     
         19 . The method of  claim 18 , wherein the forming of the first insulating layer comprises:
 forming a first upper adhesive layer on the first surface of the semiconductor chip;   forming a first filler layer on the first upper adhesive layer, the first filler layer comprising the first filler; and   forming a first lower adhesive layer on the first filler layer   wherein the forming of the second insulating layer comprises:   forming a second upper adhesive layer on the first insulating layer;   forming a second filler layer on the second upper adhesive layer, the second filler layer comprising the second filler; and   forming a second lower adhesive layer on the second filler layer.   
     
     
         20 . The method of  claim 18 , wherein the forming of the redistribution pattern hole comprises stamping the first insulating layer to form the redistribution pattern hole having a tapered shape, a cross-sectional area of which decreases in a direction towards the first surface of the semiconductor chip, and
 wherein the tapered shape comprises at least one of a triangle, a trapezoid, a stair, and a semicircle.