Memory controller

Abstract

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

1 - 20 . (canceled) 
     
     
         21 . A memory controller component comprising:
 transmit circuitry to transmit to a memory component:
 a first timing signal that requires a first time interval to propagate to the memory component; 
 write data to be sampled by the memory component synchronously with respect to the first timing signal; 
 a second timing signal that requires a second time interval to propagate to the DRAM; and 
 a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and 
   control circuitry to adjust transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.   
     
     
         22 . The memory controller component of  claim 21  wherein the second timing signal is a clock signal and the first timing signal is a strobe signal. 
     
     
         23 . The memory controller component of  claim 21  wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to render alignment, at the memory component, between respective rising edges of the first and second timing signals. 
     
     
         24 . The memory controller component of  claim 21  wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to generate a plurality of phase-distributed timing signals in response to an internal clock signal, the plurality of phase-distributed timing signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal. 
     
     
         25 . The memory controller component of  claim 24 , wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component further comprises circuitry to select at least one of the phase-distributed timing signals for transmission to the memory component as the first timing signal. 
     
     
         26 . The memory controller component of  claim 25  wherein the transmit circuitry to transmit the write data to the memory component comprises circuitry to transmit the write data synchronously with respect to the at least one of the phase-distributed timing signals selected for transmission to the memory component. 
     
     
         27 . The memory controller component of  claim 21  wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to enable the memory component to receive both the write data and the write command in a single timing domain. 
     
     
         28 . The memory controller component of  claim 21  wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals based on the difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component comprises calibration circuitry to iteratively adjust transmit timing of the at least one of the first and second timing signals in response to information indicative of phase offset between the first and second timing signals at the memory component. 
     
     
         29 . The memory controller component of  claim 27  wherein the circuitry to iteratively adjust transmit timing of the at least one of the first and second timing signals in response to the information indicative of phase offset between the first and second timing signals at the memory component comprises circuitry to incrementally advance or delay transmit timing of the at least one of the first and second timing signals in each of a sequence of timing calibration operations. 
     
     
         30 . The memory controller component of  claim 21  wherein the transmit circuitry to transmit write data to the memory component comprises a plurality of signal drivers to transmit respective bits of the write data to the memory component in parallel via respective write-data signaling links. 
     
     
         31 . A method of operation within an integrated circuit device having a memory control function, the method comprising:
 transmitting to a memory component:
 a first timing signal that requires a first time interval to propagate to the memory component; 
 write data to be sampled by the memory component synchronously with respect to the first timing signal; 
 a second timing signal that requires a second time interval to propagate to the DRAM; and 
 a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and 
   adjusting transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.   
     
     
         32 . The method of  claim 31  wherein transmitting the first timing signal to the memory component comprises transmitting a strobe signal to the memory component and wherein transmitting the second timing signal to the memory component comprises transmitting a clock signal to the memory component. 
     
     
         33 . The method of  claim 31  wherein adjusting transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises aligning, at the memory component, respective rising edges of the first and second timing signals. 
     
     
         34 . The method of  claim 31  wherein adjusting transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises generating a plurality of phase-distributed timing signals in response to an internal clock signal, the plurality of phase-distributed timing signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal. 
     
     
         35 . The method of  claim 34 , wherein adjusting transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component further comprises selecting at least one of the phase-distributed timing signals for transmission to the memory component as the first timing signal. 
     
     
         36 . The method of  claim 35  wherein transmitting the write data to the memory component comprises transmitting the write data synchronously with respect to the at least one of the phase-distributed timing signals selected for transmission to the memory component. 
     
     
         37 . The method of  claim 31  wherein adjusting transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises effecting a single timing domain within the memory component for reception of both the write data and the write command. 
     
     
         38 . The method of  claim 31  wherein adjusting transmit timing of at least one of the first and second timing signals based on the difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component comprises iteratively adjusting transmit timing of the at least one of the first and second timing signals in response to calibration information indicative of phase offset between the first and second timing signals at the memory component. 
     
     
         39 . The method of  claim 37  wherein iteratively adjusting transmit timing of the at least one of the first and second timing signals in response to the calibration information indicative of phase offset between the first and second timing signals at the memory component comprises incrementally advancing or delaying transmit timing of the at least one of the first and second timing signals in each of a sequence of timing calibration operations. 
     
     
         40 . A memory controller component comprising:
 means for transmitting to a memory component:
 a first timing signal that requires a first time interval to propagate to the memory component; 
 write data to be sampled by the memory component synchronously with respect to the first timing signal; 
 a second timing signal that requires a second time interval to propagate to the DRAM; and 
 a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and 
   means for adjusting transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.