Package structure with bump

Abstract

A package structure is provided. The package structure includes a molding layer and a first chip having a first corner and a second corner and a second chip having a third corner and a fourth corner embedded in the molding layer. The package structure also includes first bumps electrically connected to the first chip without overlapping the first chip and the second chip. In addition, the first corner and the second corner of the first chip and the third corner and the fourth corner of the second chip form a first region in a top view, and no bump overlaps the first region.

What is claimed is: 
     
         1 . A package structure, comprising:
 a molding layer;   a first chip having a first corner and a second corner and a second chip having a third corner and a fourth corner embedded in the molding layer;   first bumps electrically connected to the first chip without overlapping the first chip and the second chip, wherein the first corner and the second corner of the first chip and the third corner and the fourth corner of the second chip form a first region in a top view, and no bump overlaps the first region.   
     
     
         2 . The package structure as claimed in  claim 1 , wherein the first chip has a first sidewall connecting the first corner and the second corner, and the second chip has a second sidewall connecting the third corner and the fourth corner, and an interval between the first sidewall and the second sidewall is less than a pitch between two of the first bumps positioned next to each other. 
     
     
         3 . The package structure as claimed in  claim 2 , wherein the interval is in a range from about 50 μm to about 100 μm. 
     
     
         4 . The package structure as claimed in  claim 1 , wherein the first bumps partially surround the first chip in the top view. 
     
     
         5 . The package structure as claimed in  claim 1 , wherein the first bumps partially surround the second chip in the top view 
     
     
         6 . The package structure as claimed in  claim 1 , further comprising:
 a redistribution layer connecting the first bumps and the first chip; and   second bumps electrically connected to the first chip and the second chip through the redistribution layer and overlapping the first chip and the second chip.   
     
     
         7 . The package structure as claimed in  claim 6 , further comprising:
 first under-bump metallurgy (UBM) elements connecting to a first portion of the second bumps and overlapping the first chip in the top view; and   second UBM elements connecting to a second portion of the second bumps and overlapping the second chip in the top view,   wherein none of the first UBM elements and the second UBM elements overlaps the first region.   
     
     
         8 . The package structure as claimed in  claim 7 , wherein a shortest distance between two adjacent UBM elements of the first UBM element and the second UBM element is greater than a shortest distance between two adjacent UBM elements of the first UBM elements. 
     
     
         9 . A package structure, comprising:
 a molding layer;   a first chip having a first chip edge and a second chip having a second chip edge embedded in the molding layer, wherein a first sidewall of the first chip edge is arranged facing a second sidewall of the second chip edge;   first bumps under the molding layer and outside the first chip edge and the second chip edge in a top view,   wherein a first line of the first bumps are aligned along the first sidewall of the first chip edge and a second line of the first bumps are aligned along the second sidewall of the second chip edge in top view, and a number of the first line of the first bumps is greater than a number of the second line of the first bumps.   
     
     
         10 . The package structure as claimed in  claim 9 , wherein an interval between the first sidewall and the second sidewall is greater than a pitch between two of the first bumps positioned next to each other. 
     
     
         11 . The package structure as claimed in  claim 9 , wherein an interval between the first sidewall and the second sidewall is substantially equal to a pitch between two of the first bumps positioned next to each other. 
     
     
         12 . The package structure as claimed in  claim 9 , wherein one of a bump in the first line of the first bumps is spaced apart from the first sidewall and the second sidewall by different distances. 
     
     
         13 . The package structure as claimed in  claim 9 , further comprising:
 second bumps electrically connected to and overlapping the first chip, wherein there is a keep-out zone between the first bumps and the second bumps in the top view, and a width of the keep-out zone is in a range from about 30 μm to about 200 μm.   
     
     
         14 . A package structure, comprising:
 a molding layer;   a first chip and a second chip in the molding layer, wherein the first chip has a first chip edge, and the second chip has a second chip edge; and   first bumps under the molding layer and outside the first chip edge and the second chip edge in a top view;   wherein an interval between the first chip edge and the second chip edge is smaller than a pitch between two of the first bumps positioned next to each other.   
     
     
         15 . The package structure as claimed in  claim 14 , further comprising:
 second bumps under the molding layer and in the first chip edge in the top view; and   third bumps under the molding layer and in the first second edge in the top view,   wherein a smallest distance between the second bumps and the third bumps is greater than the interval between the first chip edge and the second chip edge.   
     
     
         16 . The package structure as claimed in  claim 14 , wherein the first bumps partially surround the first chip edge and the second chip edge in the top view. 
     
     
         17 . The package structure as claimed in  claim 14 , wherein a first group of the first bumps are aligned along a first side of the first chip edge and a first side of the second chip edge, and the first side of the first chip edge is substantially collinear with the first side of the second chip edge. 
     
     
         18 . The package structure as claimed in  claim 17 , wherein a first group of the second bumps are aligned along the first side of the first chip edge and are at opposite side of the first side of the first chip edge with the first group of the first bumps. 
     
     
         19 . The package structure as claimed in  claim 18 , wherein a first group of the third bumps are aligned along the first side of the second chip edge and are at opposite side of the first side of the second chip edge with the first group of the first bumps, wherein the first group of the second bumps are substantially collinear with the first group of the third bumps. 
     
     
         20 . The package structure as claimed in  claim 15 , wherein there is a keep-out zone around the first chip edge between the first bumps and the second bumps in the top view, and a width of the keep-out zone is in a range from about 30 μm to about 200 μm.