Memory Device Interconnects and Method of Manufacture

Abstract

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend tit rough the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

What is claimed is: 
     
         1 . A method of fabricating an integrated circuit memory device comprising:
 depositing a first dielectric layer on a substrate having a plurality of bit lines;   etching a plurality of source line trenches in the first dielectric layer and a plurality of staggered bit line contact openings in the first dielectric layer that each extend to a respective one of the plurality of bit lines;   forming a plurality of source lines in the plurality of source line trenches and a plurality of staggered bit line contacts in the plurality of staggered bit line contact openings from a first metal layer;   depositing a second dielectric layer on the first dielectric layer; and   depositing an anti-reflective coating layer on the second dielectric layer.