Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices

Abstract

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

What is claimed is: 
     
         1 . A method of forming a device, comprising:
 providing a silicon substrate with an upper surface and having first, second and third areas;   recessing the upper surface in the first and third areas of the substrate, but not in the second area of the substrate;   removing portions of the silicon substrate in the third area of the substrate to form an upwardly extending silicon fin having a pair of side surfaces extending up and terminating at a top surface;   performing a first implantation to form a first source region in the first area of the substrate;   performing a second implantation to form a first drain region in the first area of the substrate and to form a second source region and a second drain region in the third area of the substrate, wherein the first source region and the first drain region define a first channel region of the substrate extending there between, and wherein the second source region and the second drain region define a second channel region of the substrate extending there between;   performing a third implantation to form a third source region and a third drain region in the silicon fin to define a third channel region of the substrate extending there between along the top surface and the pair of side surfaces;   forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition;   forming a control gate disposed over and insulated from the floating gate using a second polysilicon deposition;   forming an erase gate disposed over and insulated from the first source region and a device gate disposed over and insulated from the second channel region using a third polysilicon deposition;   forming a word line gate disposed over and insulated from a second portion of the first channel region and a logic gate disposed over and insulated from the third channel region using a first metal deposition.   
     
     
         2 . The method of  claim 1 , wherein the removing of the portions of the silicon substrate to form the upwardly extending silicon fin is performed after the recessing. 
     
     
         3 . The method of  claim 1 , wherein the removing of the portions of the silicon substrate to form the upwardly extending silicon fin is performed before the forming of the control gate, the erase gate, the device gate, the word line gate and the logic gate. 
     
     
         4 . The method of  claim 1 , wherein the performing of the second implantation is performed after the first, second and third poly depositions. 
     
     
         5 . The method of  claim 1 , wherein the removing of the portions of the silicon substrate in the third area of the substrate to form the upwardly extending silicon fin comprises:
 forming a block of material over the third area of the substrate;   forming a spacer of material along a sidewall of the block of material;   removing the block of material;   performing an etch of the substrate around the spacer of material.   
     
     
         6 . The method of  claim 1 , wherein the logic gate is disposed vertically over and insulated from the top surface of the fin, and is disposed laterally adjacent to and insulated from the pair of side surfaces of the fin. 
     
     
         7 . The method of  claim 1 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material, and the logic gate is insulated from the third channel region by the layer of high K material. 
     
     
         8 . The method of  claim 1 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material and an oxide layer, and the logic gate is insulated from the third channel region by the layer of high K material and the oxide layer. 
     
     
         9 . The method of  claim 1 , wherein the forming of the word line gate and the logic gate comprises:
 forming a first dummy block of material over and insulated from the second portion of the first channel region and a second dummy block of material over and insulated from the third channel region using a fourth poly deposition;   removing the first and second dummy blocks of material;   forming a first block of metal material over and insulated from the second portion of the first channel region and a second block of metal material over and insulated from the third channel region.   
     
     
         10 . A device, comprising:
 a silicon substrate having an upper surface, wherein:
 the upper surface is planar in a first area and a third area of the substrate, 
 the upper surface includes an upwardly extending silicon fin in a second area of the substrate, 
 the silicon fin includes a pair of side surfaces extending up and terminating at a top surface, and 
 the upper surface of the first and third areas is recessed below the top surface of the fin; 
   a memory cell in the first area, comprising:
 spaced apart first source and first drain regions formed in the first area of substrate with a first channel region of the substrate extending there between, 
 a floating gate of polysilicon disposed over and insulated from a first portion of the first channel region, 
 a word line gate of metal disposed over and insulated from a second portion of the first channel region, 
 a control gate of polysilicon disposed over and insulated from the floating gate, and 
 an erase gate of polysilicon disposed over and insulated from the first source region; 
   a high voltage device in the third area, comprising:
 spaced apart second source and second drain regions formed in the third area of the substrate with a second channel region of the substrate extending there between, and 
 a polysilicon gate disposed over and insulated from the second channel region; 
   a logic device in the second area, comprising:
 spaced apart third source and third drain regions formed in the silicon fin with a third channel region of the substrate extending there between along the top surface and the pair of side surfaces of the silicon fin, and 
 a logic gate of metal disposed over and insulated from the third channel region. 
   
     
     
         11 . The device of  claim 10 , wherein the logic gate is disposed vertically over and insulated from the top surface of the fin, and is disposed laterally adjacent to and insulated from the pair of side surfaces of the fin. 
     
     
         12 . The device of  claim 10 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material, and the logic gate is insulated from the third channel region by the layer of high K material. 
     
     
         13 . The device of  claim 10 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material and an oxide layer, and the logic gate is insulated from the third channel region by the layer of high K material and the oxide layer.