US2021398946A1PendingUtilityA1

Semiconductor device and manufacturing method of the same

Assignee: KIOXIA CORPPriority: Jun 19, 2020Filed: Feb 26, 2021Published: Dec 23, 2021
Est. expiryJun 19, 2040(~13.9 yrs left)· nominal 20-yr term from priority
H10W 72/072H10W 95/00H10W 70/6875H10W 70/692H10W 70/611H10W 70/65H10W 42/287H10W 70/682H10W 74/142H10W 72/0198H10W 90/24H10W 90/28H10W 72/01H10W 70/099H10W 72/874H10W 72/9413H10W 90/00H10W 72/075H10W 70/09H10W 72/073H10W 70/6528H10W 72/241H10W 90/734H10W 90/736H10W 90/732H10W 42/20H10W 42/121H10W 90/701H10W 74/117H10W 74/121H10W 76/47H10W 76/153H10W 74/01H10W 74/019H10W 74/014H10W 99/00H10W 20/0698H10W 70/093H10W 70/05H10W 70/614H10W 74/129H01L 23/15H01L 2021/60022H01L 23/142H01L 25/0657H01L 21/50H01L 23/5386
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Claims

Abstract

According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a support comprising a recess;   a plurality of semiconductor chips in the recess, the semiconductor chips being stacked on each other;   a plurality of columnar electrodes in the recess, the columnar electrodes extending from the semiconductor chips toward an opening of the support;   a wiring layer over the opening of the support; and   an insulating material in the recess, the insulating material covering the semiconductor chips and the columnar electrodes.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the support comprises conductive material. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the support comprises a magnetic material. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the support comprises a resin or a ceramic. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the columnar electrodes electrically connect pads of the plurality of semiconductor chips to the wiring layer. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the support has a hardness different from a hardness of the insulating material. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the semiconductor chips are adhered to a bottom surface of the support by an adhesive layer. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the support comprises:
 a bottom portion, and   a side portion on the bottom portion.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the bottom portion and the side portion are integrally formed of the same material. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein the bottom portion and the side portion are separatable components. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein
 the semiconductor chips are stacked in tiers offset in a planar direction from one another, and   the columnar electrodes extend from tier end portions of the semiconductor chips.   
     
     
         12 . The semiconductor device according to  claim 1 , wherein the insulating material is between the semiconductor chips and the wiring layer in the recess. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the recess is filled with the insulating material. 
     
     
         14 . A method of manufacturing a semiconductor device, the method comprising:
 stacking a plurality of semiconductor chips in a recess formed in a support, the recess extending into the support from a first surface;   forming a plurality of columnar electrodes on the semiconductor chips extending upward toward an opening of the recess;   filling an insulating material into the recess to cover the semiconductor chips and the columnar electrodes with the insulating material;   polishing the insulating material until the first surface of the support and an upper end of each of the columnar electrodes are exposed; and   forming a wiring layer on the insulating material and the upper end of each of the columnar electrodes.   
     
     
         15 . The method according to  claim 14 , wherein the support has a hardness different from a hardness of the insulating material. 
     
     
         16 . The method according to  claim 14 , wherein
 the upper end of each of the columnar electrodes extend higher than the first surface of the support, and   the polishing of the insulating material exposes the upper end of each of the columnar electrodes before the first surface.   
     
     
         17 . The method according to  claim 14 , further comprising:
 electrically connecting the wiring layer to the columnar electrodes.   
     
     
         18 . A method of manufacturing a semiconductor device, the method comprising:
 stacking a plurality of semiconductor chips in a recess formed in a support, the recess extending into the support from a first surface;   covering the semiconductor chips and the first surface with an insulating material;   forming a plurality of holes in the insulating material, the holes reaching a semiconductor chip;   polishing the insulating material until the first surface of the support is exposed;   placing a metal material into the holes to form a plurality of columnar electrodes; and   forming a wiring layer on the insulating material and the columnar electrodes.   
     
     
         19 . The method according to  claim 18 , wherein the support has a hardness that is different from that of the insulating material. 
     
     
         20 . The method according to  claim 18 , further comprising:
 forming a plurality of metal bumps on the wiring layer.

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