Varied silicon richness silicon nitride formation

Abstract

A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.

1 . A non-planar memory device comprising:
 a substrate;   a stack overlaying a substrate, wherein the stack comprises multiple sacrificial nitride and inter-cell dielectric layers arranged in an alternating arrangement;   at least one opening in the stack;   a blocking dielectric layer overlying an inner surface of the at least one opening; and   a multi-layer silicon nitride structure abutting the blocking dielectric layer, wherein the multi-layer silicon nitride structure comprises:
 N layers of non-stoichiometric silicon nitride layers disposed sequentially overlying the blocking dielectric layer, wherein N is a natural number greater than 1, a first layer of the N layers abutting the first stoichiometric silicon nitride layer and an N th  layer abutting an (N−1) th  layer, wherein each of the N layers of non-stoichiometric silicon nitride layers has a silicon richness value that is mutually different from one another. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the multi-layer silicon nitride structure is terminated in response to a silicon richness value of the N th  layer of non-stoichiometric silicon nitride layers reaching a pre-determined limit. 
     
     
         3 . The apparatus of  claim 1 , further comprising a tunnel oxide layer abutting the N th  layer of non-stoichiometric silicon nitride layers. 
     
     
         4 . The apparatus of  claim 1 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers increase monotonically from the first layer to the N th  layer. 
     
     
         5 . The apparatus of  claim 1 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers decrease monotonically from the first layer to the N th  layer. 
     
     
         6 . The apparatus of  claim 1 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers increase monotonically from the first layer to an M th  layer, and the silicon richness values of the N layers of non-stoichiometric silicon nitride layers decrease monotonically from the M th  layer to the N th  layer. 
     
     
         7 . The apparatus of  claim 1 , wherein the multi-layer silicon nitride structure spans at least two memory cells of the non-planar memory device. 
     
     
         8 . A method of fabricating a non-planar memory device, the method comprising:
 forming a stack overlaying a substrate, wherein the stack comprises multiple sacrificial nitride and inter-cell dielectric layers arranged in an alternating arrangement;   etching at least one opening in the stack;   forming a blocking dielectric layer overlying an inner surface of the at least one opening; and   forming a multi-layer silicon nitride structure abutting the blocking dielectric layer, wherein the multi-layer silicon nitride structure comprises:
 N layers of non-stoichiometric silicon nitride layers disposed sequentially overlying the blocking dielectric layer, wherein N is a natural number greater than 1, a first layer of the N layers abutting the first stoichiometric silicon nitride layer and an N th  layer abutting an (N−1) th  layer, wherein each of the N layers of non-stoichiometric silicon nitride layers has a silicon richness value that is mutually different from one another. 
   
     
     
         9 . The method of  claim 8 , further comprising terminating the forming of the multi-layer silicon nitride structure in response to a silicon richness value of the N th  layer of non-stoichiometric silicon nitride layers reaching a pre-determined limit. 
     
     
         10 . The method of  claim 8 , further comprising forming a tunnel oxide layer abutting the N th  layer of non-stoichiometric silicon nitride layers. 
     
     
         11 . The method of  claim 8 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers increase monotonically from the first layer to the N th  layer. 
     
     
         12 . The method of  claim 8 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers decrease monotonically from the first layer to the N th  layer. 
     
     
         13 . The method of  claim 8 , wherein the silicon richness values of the N layers of non-stoichiometric silicon nitride layers increase monotonically from the first layer to an M th  layer, and the silicon richness values of the N layers of non-stoichiometric silicon nitride layers decrease monotonically from the M th  layer to the N th  layer. 
     
     
         14 . The method of  claim 8 , wherein the multi-layer silicon nitride structure is formed spanning at least two memory cells of the non-planar memory device.