US2022013624A1PendingUtilityA1

DRAM Capacitor Module

61
Assignee: MICROMATERIALS LLCPriority: Mar 26, 2019Filed: Sep 28, 2021Published: Jan 13, 2022
Est. expiryMar 26, 2039(~12.7 yrs left)· nominal 20-yr term from priority
H10D 1/716H10D 1/042H01L 28/91H01L 27/10808H01L 27/10852H10B 12/033H10B 12/31
61
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Claims

Abstract

Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A DRAM capacitor comprising:
 a capacitor bottom contact and a first dielectric material on a substrate;   a second dielectric material on the first dielectric material;   a fourth dielectric material on the second dielectric material;   a capacitor memory channel formed through the fourth dielectric material, the second dielectric material, and the first dielectric material; and   a capacitor formed in the capacitor memory channel,   wherein the capacitor is self-aligned with the capacitor bottom contact.   
     
     
         2 . The DRAM capacitor of  claim 1 , wherein the capacitor comprises a first conductive material, a third dielectric material on the first conductive material, and a second conductive material on the third dielectric material. 
     
     
         3 . The DRAM capacitor of  claim 1 , wherein the capacitor has a top and a bottom, and a critical dimension of the top is substantially the same as a critical dimension of the bottom. 
     
     
         4 . The DRAM capacitor of  claim 1 , wherein the first dielectric material and the second dielectric material independently comprise one or more of silicon oxide and silicon nitride. 
     
     
         5 . The DRAM capacitor of  claim 1 , wherein the capacitor bottom contact comprises one or more of a metal, a metal silicide, poly-silicon, and EPI-silicon. 
     
     
         6 . The DRAM capacitor of  claim 2 , wherein the first conductive material comprises one or more of metal mode titanium (MMTi), metal silicide, and highly doped poly-silicon. 
     
     
         7 . The DRAM capacitor of  claim 2 , wherein the third dielectric material comprises a high-κ dielectric selected from one or more of aluminum oxide, hafnium oxide, and aluminum hafnium oxide (AlHfOx). 
     
     
         8 . The DRAM capacitor of  claim 2 , wherein the second conductive material comprises one or more of poly-silicon, metal, and metal silicide.

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