Integrated Assemblies Having Void Regions Between Digit Lines and Conductive Structures, and Methods of Forming Integrated Assemblies

Abstract

Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

I/We claim: 
     
         1 . A method of forming an integrated assembly, comprising:
 forming a construction to include, along a cross-section, a pair of digit lines spaced from one another by a spacing region; each of the digit lines having a top surface, and a pair of opposing sidewall surfaces extending downwardly from the top surface; the construction including first insulative material over the top surfaces; the first insulative material and digit lines together forming beams which extend along a first direction perpendicular to the cross-section; the beams having sidewall surfaces; the digit lines having metal-containing regions; the construction including a storage-element-contact below the metal-containing regions of the digit lines and within the spacing region;   forming rails along the sidewall surfaces; each of the rails comprising a film sandwiched between a pair of panels, and comprising an insulative cap over the film and the panels; the pair of panels being an inner panel proximate one of the sidewall surfaces of the digit lines and an outer panel on an opposing side of the film from the inner panel;   etching into the outer panels to expose the film; the etching being conducted in one or more regions distal from the cross-section; after the etching, the rails retaining the configuration along the cross-section of the film between the pair of the panels and under the insulative cap;   removing at least some of the film to leave voids within the rails along the cross-section, the voids within the rails being between the panels of the rails and under the insulative caps of the rails along the cross-section;   exposing the storage-element-contact; and   forming a storage-element over the storage-element-contact and coupled with the storage-element-contact.   
     
     
         2 . The method of  claim 1  wherein the etching does not remove the insulative cap from over the film of each of the rails. 
     
     
         3 . The method of  claim 1  wherein the film of each of the rails comprises low-k material. 
     
     
         4 . The method of  claim 3  wherein the film of each of the rails comprises porous silicon dioxide. 
     
     
         5 . The method of  claim 3  wherein the film of each of the rails comprises carbon-doped silicon dioxide. 
     
     
         6 . The method of  claim 5  wherein the carbon is present in the carbon-doped silicon dioxide to a concentration within a range of from about 8 atomic percent to about 13 atomic percent. 
     
     
         7 . The method of  claim 1  wherein an entirety of the film of each of the rails is removed to form the voids. 
     
     
         8 . The method of  claim 1  wherein only some of the film of each of the rails is removed to form the voids. 
     
     
         9 . The method of  claim 1  wherein the panels and the insulative caps comprise silicon nitride. 
     
     
         10 . The method of  claim 1  wherein:
 the metal-containing regions of the digit lines have a first vertical thickness along the cross-section; and 
 the voids have a second vertical thickness which is at least about twice as large as the first vertical thickness along the cross-section. 
 
     
     
         11 . A method of forming an integrated assembly, comprising:
 forming digit lines extending along a first direction; each of the digit lines having a metal-containing region having a first vertical thickness;   forming void regions adjacent the digit lines and spaced from the digit lines by insulative spacers; the void regions extending elevationally higher than the metal-containing region, extending elevationally lower that the metal-containing region and having a second vertical thickness which is at least twice as large as the first vertical thickness;   forming conductive regions laterally spaced from the digit lines by intervening regions comprising the void regions; and   forming storage-elements associated with the conductive regions.   
     
     
         12 . The method of  claim 11  wherein the digit lines extend to a first height, and wherein the void regions extend to a second height which is at least 30 nm above the first height. 
     
     
         13 . The method of  claim 12  wherein the first vertical thickness is less than or equal to 30 nm. 
     
     
         14 . The method of  claim 11  comprising active-region-pillars extending upwardly from a base; each of the active-region-pillars having a pair of storage-element-contact-regions, and having a digit-line-contact-region between the storage-element-contact-regions; the digit lines being coupled with the digit-line-contact-regions, and the conductive regions being coupled with the storage-element-contact-regions. 
     
     
         15 . The method of  claim 14  wherein the metal-containing regions of the digit lines are coupled to the digit-line-contact-regions through conductively-doped semiconductor material. 
     
     
         16 . The method of  claim 15  wherein the conductively-doped semiconductor material comprises conductively-doped silicon. 
     
     
         17 . The method of  claim 11  wherein the storage-elements are capacitors.