Semiconductor structure and method of manufacturing thereof

Abstract

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor integrated circuit device having a top surface and an electrode extending to the top surface; and   a redistribution layer structure formed on the top surface of the semiconductor integrated circuit device, wherein the redistribution layer structure comprises:
 an oxide layer formed on the top surface; 
 a nitride layer formed on the oxide layer; 
 a dielectric layer formed on the nitride layer and having a greater thickness than a thickness of the oxide layer and the nitride layer; 
 a groove formed at a topside of the dielectric layer and overlapping the electrode; and 
 a through via formed at a bottom of the groove and extending to a portion within the electrode from the bottom of the groove through the dielectric layer, the nitride layer and the oxide layer vertically, wherein the through via and the groove are filled with a conductive material. 
   
     
     
         2 . The semiconductor structure of  claim 1 , wherein a depth of the groove is equal to or less than 25% of a thickness of the dielectric layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein a width of the through via is equal to or less than one-third of a width of the groove. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein a thickness of the dielectric layer is in a range of 8 μm to 10 μm. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising:
 an insulating layer formed on the dielectric layer, wherein a window is formed within the insulating layer to expose the groove at the topside of the dielectric layer; and   a metal layer formed on the insulating layer and filling the window to contact the conductive material.   
     
     
         6 . The semiconductor structure of  claim 5 , further comprising:
 a conductive bump formed on the metal layer.   
     
     
         7 . The semiconductor structure of  claim 5 , wherein a width of the window is less than a width of the groove.