Copper-filled trench contact for transistor performance improvement

Abstract

Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a gate electrode above a portion of a substrate, the substrate comprising silicon;   a first source or drain region adjacent a first side of the gate electrode;   a second source or drain region adjacent a second side of the gate electrode, the second side opposite the first side;   a silicide layer on the first source or drain region, the silicide layer comprising titanium;   a trench contact on the silicide layer, the trench contact in a dielectric layer and laterally adjacent the gate electrode, wherein the trench contact has a length greater than a width, and wherein the trench contact comprises:
 a barrier layer on the silicide layer, the barrier layer comprising titanium and nitrogen; and 
 a conductive material on the barrier layer, the conductive material comprising cobalt; 
   wherein the dielectric layer is over the gate electrode, and wherein a top surface of the dielectric layer is substantially co-planar with a top surface of the trench contact.   
     
     
         2 . The integrated circuit structure of  claim 1 , further comprising:
 a gate contact on the gate electrode, the gate contact having a top surface co-planar with the top surface of the dielectric layer.   
     
     
         3 . The integrated circuit structure of  claim 1 , further comprising:
 a via connector on the trench contact.   
     
     
         4 . The integrated circuit structure of  claim 3 , further comprising:
 a metallization layer on the via connector.   
     
     
         5 . The integrated circuit structure of  claim 1 , further comprising:
 a second silicide layer on the second source or drain region; and   a second trench contact on the second silicide layer.   
     
     
         6 . The integrated circuit structure of  claim 5 , further comprising:
 a via connector on the second trench contact.   
     
     
         7 . The integrated circuit structure of  claim 1 , further comprising:
 a second silicide layer on the second source or drain region;   a second trench contact on the second silicide layer;   a gate contact on the gate electrode, the gate contact having a top surface co-planar with the top surface of the dielectric layer;   a first via connector on the trench contact;   a second via connector on the second trench contact; and   a metallization layer on the first via connector.   
     
     
         8 . The integrated circuit structure of  claim 1 , wherein the trench contact length extends along an entirety of a length of the first source or drain region. 
     
     
         9 . The integrated circuit structure of  claim 1 , wherein an entirety of the trench contact width is vertically over the first source or drain region. 
     
     
         10 . The integrated circuit structure of  claim 1 , wherein the first source or drain region extends laterally beyond the trench contact. 
     
     
         11 . A method of fabricating an integrated circuit structure, the method comprising:
 forming a gate electrode above a portion of a substrate, the substrate comprising silicon;   forming a first source or drain region adjacent a first side of the gate electrode;   forming a second source or drain region adjacent a second side of the gate electrode, the second side opposite the first side;   forming a silicide layer on the first source or drain region, the silicide layer comprising titanium;   forming a trench contact on the silicide layer, the trench contact in a dielectric layer and laterally adjacent the gate electrode, wherein the trench contact has a length greater than a width, and wherein forming the trench contact comprises:
 forming a barrier layer on the silicide layer, the barrier layer comprising titanium and nitrogen; and 
 forming a conductive material on the barrier layer, the conductive material comprising cobalt; 
   wherein the dielectric layer is formed over the gate electrode, and wherein a top surface of the dielectric layer is substantially co-planar with a top surface of the trench contact.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming a gate contact on the gate electrode, the gate contact having a top surface co-planar with the top surface of the dielectric layer.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming a via connector on the trench contact.   
     
     
         14 . The method of  claim 13 , further comprising:
 forming a metallization layer on the via connector.   
     
     
         15 . The method of  claim 11 , further comprising:
 forming a second silicide layer on the second source or drain region; and   forming a second trench contact on the second silicide layer.   
     
     
         16 . The method of  claim 15 , further comprising:
 forming a via connector on the second trench contact.   
     
     
         17 . The method of  claim 11 , further comprising:
 forming a second silicide layer on the second source or drain region;   forming a second trench contact on the second silicide layer;   forming a gate contact on the gate electrode, the gate contact having a top surface co-planar with the top surface of the dielectric layer;   forming a first via connector on the trench contact;   forming a second via connector on the second trench contact; and   forming a metallization layer on the first via connector.   
     
     
         18 . The method of  claim 11 , wherein the trench contact length extends along an entirety of a length of the first source or drain region. 
     
     
         19 . The method of  claim 11 , wherein an entirety of the trench contact width is vertically over the first source or drain region. 
     
     
         20 . The method of  claim 11 , wherein the first source or drain region extends laterally beyond the trench contact.