Power semiconductor device having a structured metallization layer

Abstract

Described herein are a method and a power semiconductor device produced by the method. The power semiconductor device includes: transistor device structures formed in a semiconductor substrate; a structured metallization layer above the semiconductor substrate; a first passivation over the structured metallization layer; a second passivation on the first passivation; an opening in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation; a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.

What is claimed is: 
     
         1 . A power semiconductor device, comprising:
 a semiconductor substrate;   a plurality of transistor device structures formed in the semiconductor substrate;   a structured metallization layer above the semiconductor substrate;   a first passivation over the structured metallization layer;   a second passivation on the first passivation;   an opening formed in the first passivation and the second passivation such that a first part of the structured metallization layer has a contact region uncovered by the first passivation and the second passivation and a peripheral region laterally surrounding the contact region and covered by the first passivation and the second passivation;   a plating that covers the contact region but not the peripheral region of the first part of the structured metallization layer; and   a protective layer separating the peripheral region of the first part of the structured metallization layer from the first passivation.   
     
     
         2 . The power semiconductor device of  claim 1 , wherein the plating abuts an edge of the first passivation defined by the opening formed in the first passivation and the second passivation. 
     
     
         3 . The power semiconductor device of  claim 2 , wherein the plating abuts an edge of the second passivation defined by the opening formed in the first passivation and the second passivation. 
     
     
         4 . The power semiconductor device of  claim 1 , wherein the protective layer is between 2 nm and 20 nm thick, wherein the first passivation is between 40 nm and 5 μm thick, and wherein the plating is between 500 nm and 5 μm thick. 
     
     
         5 . The power semiconductor device of  claim 1 , wherein the protective layer is configured to prevent silicide formation, and/or prevent migration of metal, and/or promote adhesion between metal of the metallization and the first passivation. 
     
     
         6 . The power semiconductor device of  claim 1 , wherein the protective layer comprises at least one of aluminum oxide, zirconium oxide, silicon oxide, silicon nitride, and boron nitride. 
     
     
         7 . The power semiconductor device of  claim 1 , wherein the first passivation comprises a first silicon nitride layer on the protective layer and an oxide layer on the first silicon nitride layer. 
     
     
         8 . The power semiconductor device of  claim 7 , wherein the first passivation further comprises a second silicon nitride layer on the oxide layer. 
     
     
         9 . The power semiconductor device of  claim 1 , wherein the first passivation comprises an oxide layer on the protective layer and a silicon nitride layer on the oxide layer. 
     
     
         10 . The power semiconductor device of  claim 1 , wherein the first passivation and the second passivation cover a sidewall and a top surface of the peripheral region. 
     
     
         11 . The power semiconductor device of  claim 1 , wherein the semiconductor substrate is a SiC substrate or a GaN substrate. 
     
     
         12 . The power semiconductor device of  claim 1 , wherein the plating is a sinterable, solderable or wire-bondable material. 
     
     
         13 . The power semiconductor device of  claim 12 , wherein the sinterable or solderable material comprises Ni, NiP, NiMoP, Pd, Ag, or Au. 
     
     
         14 . The power semiconductor device of  claim 1 , wherein the protective layer is between 2 nm and 20 nm thick, and wherein the first passivation is between 40 nm and 5 um thick. 
     
     
         15 . The power semiconductor device of  claim 1 , wherein the structured metallization layer is a structured Cu layer, a structured AlCu layer, a structured Ag layer, or a structured Au layer. 
     
     
         16 . The power semiconductor device of  claim 1 , wherein the structured metallization layer comprises Cu, and wherein the protective layer prevents copper silicidation of the structured metallization. 
     
     
         17 . The power semiconductor device of  claim 1 , wherein a second part of the structured metallization layer is exposed and plated in a different region of the power semiconductor device than the first part of the structured metallization layer. 
     
     
         18 . The power semiconductor device of  claim 17 , wherein the second part of the structured metallization layer provides a gate signal connection for the power semiconductor device. 
     
     
         19 . The power semiconductor device of  claim 17 , wherein the second part of the structured metallization layer provides a field plate connection to a gate electrode structure included in the power semiconductor device. 
     
     
         20 . The power semiconductor device of  claim 17 , wherein the second part of the structured metallization layer provides a field plate connection to an edge termination structure included in the power semiconductor device.