Semiconductor device with reduced via resistance

Abstract

A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor interconnect structure, comprising:
 a metal capping layer disposed over a metal line, the metal line disposed in a first dielectric layer;   a dielectric capping layer disposed on the first dielectric layer; and   a second dielectric layer disposed on the metal capping layer and the dielectric capping layer, wherein a top surface of the metal capping layer is substantially co-planar with a top surface of the dielectric capping layer.   
     
     
         21 . The semiconductor interconnect structure of  claim 20 , wherein the metal capping layer comprises at least one of Co or Ru. 
     
     
         22 . The semiconductor interconnect structure of  claim 20 , wherein the metal capping layer comprises Rh. 
     
     
         23 . The semiconductor interconnect structure of  claim 20 , wherein the metal capping layer comprises at least one of W or P. 
     
     
         24 . The semiconductor interconnect structure of  claim 20 , wherein the dielectric capping layer comprises C. 
     
     
         25 . The semiconductor interconnect structure of  claim 24 , wherein the metal capping layer and the dielectric capping layer have a thickness between 15 nm and 55 nm. 
     
     
         26 . The semiconductor interconnect structure of  claim 20 , wherein the metal capping layer and the dielectric capping layer have a thickness between 25 nm and 45 nm. 
     
     
         27 . The semiconductor interconnect structure of  claim 20 , wherein a via opening is disposed in the second dielectric layer. 
     
     
         28 . The semiconductor interconnect structure of  claim 27 , further comprising a liner disposed in the via opening. 
     
     
         29 . The semiconductor interconnect structure of  claim 28 , wherein the liner comprises Co. 
     
     
         30 . The semiconductor interconnect structure of  claim 28 , wherein the liner comprises Ru. 
     
     
         31 . The semiconductor interconnect structure of  claim 28 , wherein the liner comprises Mn. 
     
     
         32 . The semiconductor interconnect structure of  claim 20 , further comprising a first liner disposed on one or more sidewalls of a via opening, wherein the one or more sidewalls comprise at least a portion of each of the second dielectric layer, the dielectric capping layer, and the metal capping layer. 
     
     
         33 . The semiconductor interconnect structure of  claim 32 , further comprising a conductive material disposed in the via opening, wherein the conductive material directly contacts the metal line and the first liner. 
     
     
         34 . The semiconductor interconnect structure of  claim 32 , wherein the first liner is discontinuous at a bottom surface of the via opening. 
     
     
         35 . The semiconductor interconnect structure of  claim 34 , further comprising a second liner disposed on the first liner. 
     
     
         36 . The semiconductor interconnect structure of  claim 35 , wherein the second liner directly contacts the metal line. 
     
     
         37 . The semiconductor interconnect structure of  claim 32 , wherein the first liner is discontinuous along a surface of the dielectric capping layer. 
     
     
         38 . The semiconductor interconnect structure of  claim 37 , further comprising a second liner disposed on the first liner. 
     
     
         39 . The semiconductor interconnect structure of  claim 38 , wherein the second liner directly contacts the dielectric capping layer. 
     
     
         40 . The semiconductor interconnect structure of  claim 20 , further comprising an electrically conductive structure disposed in the second dielectric layer, wherein the electrically conductive structure contacts the metal capping layer and the dielectric capping layer and is in electrical contact with the metal line. 
     
     
         41 . A semiconductor interconnect structure, comprising:
 a first electrically conductive structure embedded in a first dielectric layer;   a metal capping layer disposed on at least a portion of the first electrically conductive structure;   a dielectric capping layer disposed on at least a portion of the first dielectric layer, wherein a top surface of the metal capping layer is substantially co-planar with a top surface of the dielectric capping layer;   a second dielectric layer disposed on the metal capping layer and the dielectric capping layer; and   a second electrically conductive structure disposed in the second dielectric layer, wherein the second electrically conductive structure contacts the dielectric capping layer and is in electrical contact with the first electrically conductive structure.