Semiconductor Package with Lead Tip Inspection Feature

Abstract

A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices each of the sidewall-facing terminals is electrically connected to the semiconductor die of the respective packaged semiconductor device. Each of the sidewall-facing terminals of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

What is claimed is: 
     
         1 . A packaged semiconductor device, comprising:
 a semiconductor die comprising a plurality of bond pads;   an encapsulant body of electrically insulating encapsulant material that encapsulates the semiconductor die;   a plurality of sidewall-facing terminals disposed on a sidewall of the encapsulant body,   wherein the sidewall-facing terminal is electrically connected to one of the bond pads;   wherein the sidewall-facing terminal extends completely between top and bottom surfaces of the encapsulant body, and   wherein the electrically insulating encapsulant material comprises a laser activatable mold compound.   
     
     
         2 . The packaged semiconductor device of  claim 1 , wherein each of the sidewall-facing terminals continuously extend from the sidewall of the encapsulant body to a main surface of the encapsulant body that intersects with the sidewall of the encapsulant body. 
     
     
         3 . The packaged semiconductor device of  claim 2 , wherein the packaged semiconductor device comprises a notch in the sidewall of the encapsulant body that extends between the top and bottom surfaces, and wherein each of the sidewall-facing terminals is disposed within the notch. 
     
     
         4 . The packaged semiconductor device of  claim 1 , wherein the packaged semiconductor device is configured as an integrated circuit. 
     
     
         5 . The packaged semiconductor device of  claim 1 , wherein the encapsulant body comprises a first mold compound material that encapsulates the semiconductor die, and wherein the laser-activatable mold compound is formed on the first mold compound material such that the laser-activatable mold compound is exposed at outer surfaces of the encapsulant body. 
     
     
         6 . The packaged semiconductor device of  claim 1 , wherein a rear surface of the semiconductor die is exposed at the bottom surface of the encapsulant body. 
     
     
         7 . The packaged semiconductor device of  claim 1 , wherein a rear surface of the semiconductor die is covered by the encapsulant body. 
     
     
         8 . The packaged semiconductor device of  claim 1 , wherein the sidewall of the encapsulant body outside of each of the sidewall-facing terminals is substantially coplanar to each of the sidewall-facing terminals. 
     
     
         9 . The packaged semiconductor device of  claim 1 , wherein each of the sidewall-facing terminals is formed on a laser activated region of the laser activatable mold compound. 
     
     
         10 . The packaged semiconductor device of  claim 9 , wherein the sidewall of the encapsulant body between pairs of the sidewall-facing terminals is not laser activated.