Semiconductor memory device

Abstract

Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a substrate comprising an NMOS region and a PMOS region;   a first gate pattern on the NMOS region of the substrate; and   a second gate pattern on the PMOS region of the substrate,   wherein the first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate,   the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate,   the diffusion mitigation pattern is in contact with the first high-k layer,   a stacked structure of the first gate electrode is same as that of the second gate electrode, and   the second gate pattern does not comprise the N-type work function pattern.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein
 the first gate pattern comprises a first conductive pattern between the N-type work function pattern and the first gate electrode, and   the second gate pattern comprises a second conductive pattern between the second high-k layer and the second gate electrode.   
     
     
         3 . The semiconductor memory device of  claim 2 , wherein a vertical length of the first conductive pattern and a vertical length of the second conductive pattern are equal to each other. 
     
     
         4 . The semiconductor memory device of  claim 2 , wherein a vertical length of the first conductive pattern is less than a vertical length of the second conductive pattern. 
     
     
         5 . The semiconductor memory device of  claim 2 , wherein
 the second conductive pattern is a single layer, and   the second conductive pattern is shared with at least a part of the first conductive pattern.   
     
     
         6 . The semiconductor memory device of  claim 1 , wherein the second gate pattern comprises a P-type work function pattern between the second high-k layer and the second gate electrode. 
     
     
         7 . The semiconductor memory device of  claim 6 , wherein the first gate pattern comprises the P-type work function pattern. 
     
     
         8 . The semiconductor memory device of  claim 1 , wherein the first gate pattern comprises a boundary pattern at a boundary between the N-type work function pattern and the diffusion mitigation pattern. 
     
     
         9 . The semiconductor memory device of  claim 8 , wherein the boundary pattern comprises at least one of lanthanum titanium nitride or lanthanum titanium oxynitride. 
     
     
         10 . The semiconductor memory device of  claim 1 , wherein the diffusion mitigation pattern is in contact with the N-type work function pattern, and is a single layer comprising titanium nitride. 
     
     
         11 . The semiconductor memory device of  claim 1 , wherein the N-type work function pattern comprises at least one of lanthanum (La), lanthanum oxide (LaO), magnesium (Mg), magnesium oxide (MgO), tantalum (Ta), tantalum nitride (TaN), or niobium (Nb). 
     
     
         12 . The semiconductor memory device of  claim 1 , further comprising:
 a first gate capping pattern on the first gate pattern; and   a second gate capping pattern on the second gate pattern,   wherein a top surface of the first gate capping pattern is on a same plane as a top surface of the second gate capping pattern.   
     
     
         13 . The semiconductor memory device of  claim 1 , further comprising, in the PMOS region, a channel layer between the substrate and the second high-k layer and comprising silicon germanium. 
     
     
         14 . A semiconductor memory device comprising:
 a substrate comprising first to fourth peripheral regions;   first to fourth peripheral insulating layers respectively on the first to fourth peripheral regions of the substrate, the first peripheral insulating layer thicker than the second peripheral insulating layer, the third peripheral insulating layer thicker than the fourth peripheral insulating layer;   first to third peripheral gate patterns respectively on the first to third peripheral insulating layers;   a channel layer between the substrate of the fourth peripheral region and the fourth peripheral insulating layer, the channel layer comprising silicon germanium; and   a fourth peripheral gate pattern on the channel layer,   wherein the first peripheral gate pattern comprises a first peripheral high-k layer, a first peripheral diffusion mitigation pattern, a first peripheral N-type work function pattern, and a first peripheral gate electrode, which are sequentially stacked on the substrate,   the second peripheral gate pattern comprises a second peripheral high-k layer, a second peripheral diffusion mitigation pattern, a second peripheral N-type work function pattern, and a second peripheral gate electrode, which are sequentially stacked on the substrate,   the third peripheral gate pattern comprises a third peripheral high-k layer and a third peripheral gate electrode which are sequentially stacked on the substrate,   the fourth peripheral gate pattern comprises a fourth peripheral high-k layer and a fourth peripheral gate electrode which are sequentially stacked on the channel layer,   the first peripheral diffusion mitigation pattern is in contact with the first peripheral high-k layer,   the second peripheral diffusion mitigation pattern is in contact with the second peripheral high-k layer,   the first to fourth peripheral gate electrodes have a same stacked structure, and   the third and fourth peripheral gate patterns do not comprise the first and second peripheral N-type work function patterns.   
     
     
         15 . The semiconductor memory device of  claim 14 , wherein
 the first and second peripheral regions are NMOS regions, and   the third and fourth peripheral regions are PMOS regions.   
     
     
         16 . The semiconductor memory device of  claim 14 , wherein the first peripheral gate pattern further comprises a peripheral boundary pattern at a boundary between the first peripheral diffusion mitigation pattern and the first peripheral N-type work function pattern. 
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the peripheral boundary pattern comprises at least one of lanthanum titanium nitride or lanthanum titanium oxynitride. 
     
     
         18 . The semiconductor memory device of  claim 14 , wherein each of the first and second peripheral diffusion mitigation patterns is a single layer. 
     
     
         19 . A semiconductor memory device comprising:
 a substrate comprising a cell array region, a first peripheral region, and a second peripheral region;   a bit line crossing the substrate in the cell array region;   a buffer layer between the bit line and the substrate;   a first peripheral gate pattern on the first peripheral region of the substrate; and   a second peripheral gate pattern on the second peripheral region of the substrate,   wherein the first peripheral gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate,   the second peripheral gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate,   the diffusion mitigation pattern is in contact with the first high-k layer,   the first gate electrode, the second gate electrode, and the bit line have a same stacked structure, and   the second peripheral gate pattern does not comprise the N-type work function pattern.   
     
     
         20 . The semiconductor memory device of  claim 19 , further comprising:
 a bit line capping pattern on the bit line; and   a gate capping pattern on the first gate electrode,   wherein a vertical length of the bit line capping pattern is greater than a vertical length of the gate capping pattern.