Apparatuses, methods, and systems to precisely monitor memory store accesses

Abstract

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

1 .- 24 . (canceled) 
     
     
         25 . An apparatus comprising:
 a memory;   a hardware processor core comprising:
 a decoder to decode an instruction into a decoded instruction, 
 an execution circuit to execute the decoded instruction to produce a resultant, 
 a first level data cache, 
 a store buffer, and 
 a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit that missed in the first level data cache is queued into the store buffer for storage into the memory but is not yet completed within the memory; and 
   a performance monitoring circuit to:
 monitor post-retirement performance information of the retired instruction between the store request being accepted into the first level data cache and being completed in the memory, and 
 store the post-retirement performance information in storage of the performance monitoring circuit. 
   
     
     
         26 . The apparatus of  claim 25 , wherein the performance monitoring circuit is to monitor and store in response to the performance monitoring circuit being in precise event-based sampling mode. 
     
     
         27 . The apparatus of  claim 25 , wherein, when the store request is accepted into the first level data cache, the performance monitoring circuit is to enable a counter to measure a latency between the store request being accepted into the first level data cache and being completed in the memory, and the post-retirement performance information comprises the latency from the counter. 
     
     
         28 . The apparatus of  claim 25 , wherein the post-retirement performance information comprises a value to indicate the store request missed in the first level data cache. 
     
     
         29 . The apparatus of  claim 25 , wherein the memory is another level of cache. 
     
     
         30 . The apparatus of  claim 25 , wherein the memory is a system memory coupled to the hardware processor core and separate from any cache of the hardware processor core. 
     
     
         31 . The apparatus of  claim 30 , wherein the post-retirement performance information comprises at least one value to indicate the store request missed in the first level data cache and missed in a translation lookaside buffer of another level of cache. 
     
     
         32 . The apparatus of  claim 25 , wherein the post-retirement performance information comprises a value to indicate the store request is a locked access. 
     
     
         33 . The apparatus of  claim 25 , wherein the post-retirement performance information comprises a linear address of a destination in the memory of the store request. 
     
     
         34 . A method comprising:
 decoding an instruction into a decoded instruction with a decoder of a hardware processor core coupled to a memory, the hardware processor core comprising a first level data cache and a store buffer;   executing the decoded instruction with an execution circuit of the hardware processor core to produce a resultant;   retiring the instruction with a retirement circuit of the hardware processor core when a store request for the resultant from the execution circuit that missed in the first level data cache is queued into the store buffer for storage into the memory but is not yet completed within the memory;   monitoring, by a performance monitoring circuit of the hardware processor core, post-retirement performance information of the retired instruction between the store request being accepted into the first level data cache and being completed in the memory; and   storing, by the performance monitoring circuit, the post-retirement performance information in storage of the performance monitoring circuit.   
     
     
         35 . The method of  claim 34 , wherein the monitoring and storing occurs in response to the performance monitoring circuit being in precise event-based sampling mode. 
     
     
         36 . The method of  claim 34 , further comprising, when the store request is accepted into the first level data cache, enabling, by the performance monitoring circuit, a counter to measure a latency between the store request being accepted into the first level data cache and being completed in the memory, wherein the post-retirement performance information comprises the latency from the counter. 
     
     
         37 . The method of  claim 34 , wherein the post-retirement performance information comprises a value to indicate the store request missed in the first level data cache. 
     
     
         38 . The method of  claim 34 , wherein the memory is another level of cache. 
     
     
         39 . The method of  claim 34 , wherein the memory is a system memory coupled to the hardware processor core and separate from any cache of the hardware processor core. 
     
     
         40 . The method of  claim 39 , wherein the post-retirement performance information comprises at least one value to indicate the store request missed in the first level data cache and missed in a translation lookaside buffer of another level of cache. 
     
     
         41 . The method of  claim 34 , wherein the post-retirement performance information comprises a value to indicate the store request is a locked access. 
     
     
         42 . The method of  claim 34 , wherein the post-retirement performance information comprises a linear address of a destination in the memory of the store request. 
     
     
         43 . A system comprising:
 a memory coupled to a hardware processor core and separate from the hardware processor core;   the hardware processor core comprising:
 a decoder to decode an instruction into a decoded instruction, 
 an execution circuit to execute the decoded instruction to produce a resultant, 
 a first level data cache, 
 a store buffer, and 
 a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit that missed in the first level data cache is queued into the store buffer for storage into the memory but is not yet completed within the memory; and 
   a performance monitoring circuit to:
 monitor post-retirement performance information of the retired instruction between the store request being accepted into the first level data cache and being completed in the memory, and 
 store the post-retirement performance information in storage of the performance monitoring circuit. 
   
     
     
         44 . The system of  claim 43 , wherein the performance monitoring circuit is to monitor and store in response to the performance monitoring circuit being in precise event-based sampling mode. 
     
     
         45 . The system of  claim 43 , wherein, when the store request is accepted into the first level data cache, the performance monitoring circuit is to enable a counter to measure a latency between the store request being accepted into the first level data cache and being completed in the memory, and the post-retirement performance information comprises the latency from the counter. 
     
     
         46 . The system of  claim 43 , wherein the post-retirement performance information comprises a value to indicate the store request missed in the first level data cache. 
     
     
         47 . The system of  claim 43 , wherein the memory is another level of cache separate from the hardware processor core. 
     
     
         48 . The system of  claim 43 , wherein the memory is a system memory coupled to the hardware processor core and separate from any cache of the system. 
     
     
         49 . The system of  claim 48 , wherein the post-retirement performance information comprises at least one value to indicate the store request missed in the first level data cache and missed in a translation lookaside buffer of another level of cache. 
     
     
         50 . The system of  claim 43 , wherein the post-retirement performance information comprises a value to indicate the store request is a locked access. 
     
     
         51 . The system of  claim 43 , wherein the post-retirement performance information comprises a linear address of a destination in the memory of the store request.