Semiconductor package interconnect and power connection by metallized structures on package body

Abstract

A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.

What is claimed is: 
     
         1 . A method of forming a packaged semiconductor device, the method comprising:
 providing a lead frame comprising a die pad and a plurality of leads;   providing a first semiconductor die that comprises a first load terminal disposed on a main surface of the first semiconductor die;   providing a second semiconductor die that comprises a plurality of I/O terminals disposed on a main surface of the second semiconductor die,   mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies each face away from the die pad;   forming an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies;   forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals from the second semiconductor die to a first group of the leads; and   forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.   
     
     
         2 . The method of  claim 1 , wherein the encapsulant body is formed to expose interior surface portions of the leads at the upper surface of the encapsulant body, wherein the conductive tracks are formed to contact the interior surface portions of the leads from the first group of the leads, and wherein the metal pad is formed to contact the interior surface portion of the second lead. 
     
     
         3 . The method of  claim 2 , wherein the encapsulant body is formed to comprise a depression in the upper surface of the encapsulant body, and wherein the exposed interior surface portions of the leads protrude out from a first sidewall of the depression. 
     
     
         4 . The method of  claim 2 , further comprising forming vertical interconnect elements on the I/O terminals of the second semiconductor die before forming the encapsulant body, wherein the encapsulant body is formed to expose upper ends of the vertical interconnect elements that are disposed on the I/O terminals at the upper surface of the encapsulant body, and wherein the conductive tracks are formed to contact the exposed upper ends of the vertical interconnect elements that are disposed on the I/O terminals. 
     
     
         5 . The method of  claim 2 , wherein forming either one of the plurality of conductive tracks and the metal pad comprises any one or more of:
 laser assisted metal deposition;   inkjet metal printing;   electroplating; and   electroless plating.   
     
     
         6 . The method of  claim 2 , further comprising forming vertical interconnect elements on the first load terminal of the first semiconductor die before forming encapsulant body, and wherein the encapsulant body is formed to expose upper ends of the vertical interconnect elements on the first load terminal at the upper surface of the encapsulant body. 
     
     
         7 . The method of  claim 6 , wherein the metal pad is formed on the upper surface of the encapsulant body so as to contact the exposed upper ends of the vertical interconnect elements on the first load terminal. 
     
     
         8 . The method of  claim 6 , further comprising forming an opening in the upper surface of the encapsulant body that exposes the first load terminal of the first semiconductor die, and wherein forming the opening comprises using the exposed upper ends of the vertical interconnect elements on the first load terminal to identify a location of the first load terminal underneath the encapsulant body. 
     
     
         9 . The method of  claim 2 , further comprising forming a ribbon on the first load terminal of the first semiconductor die before forming encapsulant body, wherein the encapsulant body is formed to expose apex points of the ribbon at the upper surface of the encapsulant body, and wherein the metal pad is formed on the exposed apex points of the ribbon. 
     
     
         10 . The method of  claim 2 , further comprising forming a solder mask over the conductive tracks. 
     
     
         11 . The method of  claim 2 , further comprising forming a layer of electrically insulating and thermally conductive material that covers the metal pad. 
     
     
         12 . The method of  claim 1 , wherein the encapsulant body is formed to directly expose the first load terminal and the I/O terminals at the first surface of the encapsulant body. 
     
     
         13 . The method of  claim 1 , wherein the first semiconductor die is a power transistor die that comprises a gate terminal disposed on the main surface of the first semiconductor die, wherein the second semiconductor die is a logic die, and wherein the method further comprises:
 forming a second conductive track on the upper surface of the encapsulant body that electrically connects one of the I/O terminals from the second semiconductor die to the gate terminal of the first semiconductor die.   
     
     
         14 . The method of  claim 13 , wherein the first semiconductor die comprises a second load terminal that is disposed on a rear surface of the first semiconductor die, wherein the second load terminal of the first semiconductor die faces and electrically connects with the die pad. 
     
     
         15 . A method of forming a packaged semiconductor device, the method comprising:
 providing a lead frame comprising a die pad and a plurality of leads;   providing a first semiconductor die that comprises a first load terminal and a plurality of I/O terminals disposed on a main surface of the first semiconductor die;   providing a second semiconductor die that comprises a first load terminal and a gate terminal disposed on a main surface of the second semiconductor die;   mounting the first semiconductor die directly on the lead frame such that the main surface of the first semiconductor die faces away from the lead frame;   mounting the second semiconductor die on the first semiconductor die such that the main surface of the second semiconductor die faces away from the lead frame;   forming an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies;   forming a plurality of first conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals from the first semiconductor die to a first group of the leads;   forming a second conductive track on the upper surface of the encapsulant body that electrically connects one of the I/O terminals from the first semiconductor die to the gate terminal of the second semiconductor die;   forming a first metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal of the first semiconductor die to a second lead; and   forming a second metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal of the second semiconductor die to a third lead.   
     
     
         16 . The method of  claim 15 , wherein the first semiconductor die comprises a power transistor device block and a logic block monolithically integrated in the first semiconductor die, wherein the second transistor die comprises a power transistor device, wherein the power transistor device block of the first semiconductor die and the power transistor device of the second semiconductor die form a half-bridge circuit, and wherein the logic block of the first semiconductor die forms a driver circuit that is configured to control a switching operation of the half-bridge circuit. 
     
     
         17 . The method of  claim 16 , further comprising:
 providing a third semiconductor die that comprises a first load terminal and a plurality of I/O terminals disposed on a main surface of the third semiconductor die;   providing a fourth semiconductor die that comprises a first load terminal and a gate terminal disposed on a main surface of the fourth semiconductor die;   mounting the third semiconductor die directly on the lead frame such that the main surface of the third semiconductor die faces away from the lead frame; and   mounting the fourth semiconductor die on the third semiconductor die such that the main surface of the fourth semiconductor die faces away from the lead frame;   
       wherein the third semiconductor die comprises a power transistor device block and a logic block monolithically integrated in the third semiconductor die, wherein the fourth transistor die comprises a power transistor device, wherein the power transistor device block of the third semiconductor die and the power transistor device of the fourth semiconductor die form a second half-bridge circuit, and wherein the logic block of the third semiconductor die forms a driver circuit that is configured to control a switching operation of the second half-bridge circuit. 
     
     
         18 . A packaged semiconductor device, comprising:
 a lead frame comprising a die pad and a plurality of leads;   a first semiconductor die that comprises a first load terminal disposed on a main surface of the first semiconductor die that faces away from the die pad;   a second semiconductor die that comprises a plurality of I/O terminals disposed on a main surface of the second semiconductor die that faces away from the die pad;   an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies;   a plurality of conductive tracks that are formed on an upper surface of the encapsulant body and electrically connect at least some of the I/O terminals from the second semiconductor die to a first group the leads; and   a metal pad formed on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.   
     
     
         19 . The packaged semiconductor device of  claim 18 , wherein interior surface portions of the leads are exposed at the upper surface of the encapsulant body, and wherein the metal pad and the conductive tracks contact the exposed interior surface portions of the leads. 
     
     
         20 . The packaged semiconductor device of  claim 19 , wherein the encapsulant body comprises a depression in the upper surface of the encapsulant body, and wherein the exposed interior surface portions of the leads protrude out from a first outer sidewall of the depression. 
     
     
         21 . The packaged semiconductor device of  claim 20 , wherein the depression is spaced apart from an outer edge side of the encapsulant body by a thicker portion of the of the encapsulant body, and wherein upper surfaces of the leads are covered by encapsulant material in the thicker portion. 
     
     
         22 . The packaged semiconductor device of  claim 21 , wherein the depression comprises a second sidewall that is opposite from the first sidewall and a bottom surface, and wherein the metal pad completely fills a region between the first and second sidewalls of the depression. 
     
     
         23 . The packaged semiconductor device of  claim 18 , wherein the first semiconductor die is a power transistor die that comprises a gate terminal disposed on the main surface of the first semiconductor die, wherein the second semiconductor die is a logic die, and wherein the semiconductor package further comprises a second plurality of conductive tracks on the upper surface of the encapsulant body that electrically connect at least one of the I/O terminals from the second semiconductor die to the gate terminal of the second semiconductor die. 
     
     
         24 . The packaged semiconductor device of  claim 18 , wherein the first semiconductor die is mounted on top of the second semiconductor die, and wherein the second semiconductor die is mounted directly on the die pad.