Methods of forming dislocation enhanced strain in nmos and pmos structures

Abstract

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

1 . A fin Field Effect Transistor (finFET) comprising:
 a single-crystal semiconductor substrate;   a finFET body extending from the single-crystal semiconductor substrate, the finFET body having a top and laterally opposite sidewalls extending from a source side to a drain side, the laterally opposite sidewalls adjacent to isolation regions;   a gate dielectric over the top and laterally opposite sidewalls of the finFET body;   a gate electrode over the gate dielectric;   sidewall spacers formed on the source and drain sides of the finFET body;   dislocation nucleation material selectively grown using epitaxial grown upon source and drain recesses laterally adjacent to the source and drain sides of the finFET body, respectively, the dislocation nucleation material in contact with a surface of the dielectric spacers and with a surface of the gate dielectric, wherein the dislocation nucleation material comprises silicon-germanium;   source and drains materials formed on the silicon-germanium dislocation nucleation layers, the source and drain materials having dislocations extending from the dislocation nucleation layers; wherein the dislocation material further comprises phosphorus and/or arsenic, wherein the phosphorus and/or arsenic has a concentration between 10 16  cm −3  and 10 21 cm −3 ; and wherein a lattice constant of the dislocation nucleation material is between 5.43 Å and 5.66 Å.   
     
     
         2 . The finFET of  claim 1 , wherein the germanium concentration of the silicon-germanium is between 10 and 80 atomic percent. 
     
     
         3 . The finFET of  claim 1 , wherein the dislocation nucleation material induces a tensile stress in a channel region along a conduction direction. 
     
     
         4 . The finFET of  claim 1 , wherein the source and drain materials comprise silicon and phosphorus. 
     
     
         5 . The finFET of  claim 1 , wherein the dislocation nucleation material comprises a lower portion comprising silicon germanium, phosphorus, and/or arsenic and an upper portion comprising silicon and phosphorus. 
     
     
         6 . The finFET of  claim 1 , further comprising:
 a nano-wire structure.   
     
     
         7 . The finFET of  claim 6 , wherein the nano-wire structure comprises wrap-around nanowire material disposed underneath the gate dielectric. 
     
     
         8 . The finFET of  claim 7 , wherein the nano-wire structure further comprises a wrap-around gate dielectric disposed beneath the wrap-around nanowire material. 
     
     
         9 . The finFET of  claim 8 , wherein the nano-wire structure further comprises a wrap-around gate electrode disposed underneath the wrap-around gate dielectric. 
     
     
         10 . The finFET of  claim 1 , wherein a top of the source material is spaced apart from a top of the drain material by a first distance, and a bottom of the source material is spaced apart from a bottom of the drain material by a second distance greater than the first distance.