Three-dimensional metal-insulator-metal capacitor embedded in seal structure

Abstract

Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

What is claimed is: 
     
         1 . A method for forming an integrated circuit, the method comprising:
 forming a substrate comprising an interior region and an edge region surrounding an outer perimeter of the interior region of a chip; and   forming a seal ring in the edge region, the seal ring comprising a plurality of metal-insulator-metal (MIM) capacitors;   wherein each of the MIM capacitors comprises two or more plates and one or more dielectric layers, wherein each dielectric layer is positioned between an adjacent pair of the two or more plates; and   wherein a portion of the two or more plates extends over an interconnect in the interior region of the substrate.   
     
     
         2 . The method of  claim 1 , wherein each of the MIM capacitors is configured both as a decoupling capacitor and as a crack stop. 
     
     
         3 . The method of  claim 1 , wherein the seal ring further comprises an outer wall and an inner wall. 
     
     
         4 . The method of  claim 3 , wherein each of the MIM capacitors is positioned between the outer wall and the inner wall. 
     
     
         5 . The method of  claim 1 , wherein each of the MIM capacitors is electrically coupled to a last metal wiring level of the interconnect. 
     
     
         6 . An integrated circuit comprising:
 a substrate comprising an interior region and an edge region surrounding an outer perimeter of the interior region of a chip; and   a seal ring in the edge region, the seal ring comprising a plurality of metal-insulator-metal (MIM) capacitors;   wherein each of the MIM capacitors comprises two or more plates and one or more dielectric layers, wherein each dielectric layer is positioned between an adjacent pair of the two or more plates; and   wherein a portion of the two or more plates extends over an interconnect in the interior region of the substrate.   
     
     
         7 . The integrated circuit of  claim 6 , wherein each of the MIM capacitors is configured both as a decoupling capacitor and as a crack stop. 
     
     
         8 . The integrated circuit of  claim 6 , wherein the seal ring further comprises an outer wall and an inner wall. 
     
     
         9 . The integrated circuit of  claim 8 , wherein each of the MIM capacitors is positioned between the outer wall and the inner wall. 
     
     
         10 . The integrated circuit of  claim 6 , wherein each of the MIM capacitors is electrically coupled to a last metal wiring level of the interconnect. 
     
     
         11 . The integrated circuit of  claim 10 , wherein a first plate of a first MIM capacitor of the plurality of MIM capacitors is electrically coupled to the last metal wiring level of the interconnect. 
     
     
         12 . The integrated circuit of  claim 11 , wherein a second plate of the first MIM capacitor of the plurality of MIM capacitors is electrically isolated from the last metal wiring level of the interconnect.