METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES

Abstract

A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a substrate comprising a substrate semiconductor material;   a first finFET formed on the substrate and comprising a first fin having a lower portion comprising the substrate semiconductor material and an upper portion of a first semiconductor material;   a second finFET formed on the substrate and comprising a second fin having a lower portion comprising the substrate semiconductor material and an upper portion of a second semiconductor material different from the first semiconductor material; and   a third finFET formed on the substrate and comprising a third fin having a lower portion comprising the substrate semiconductor material and an upper portion of a third semiconductor material different from the first and second semiconductor materials.   
     
     
         2 . The integrated circuit of  claim 1 , wherein:
 the substrate semiconductor material is Si;   the first semiconductor material comprises Si;   the second semiconductor material comprises SiGe; and   the third semiconductor material comprises one of SiC, GaAs, and AlGaAs.   
     
     
         3 . The integrated circuit of  claim 2 , wherein the third semiconductor material comprises SiC. 
     
     
         4 . The integrated circuit of  claim 2 , wherein the third semiconductor material comprises GaAs. 
     
     
         5 . The integrated circuit of  claim 2 , wherein the third semiconductor material comprises AlGaAs. 
     
     
         6 . The integrated circuit of  claim 2 , wherein the first semiconductor material is Si doped with a first dopant such that the first finFET is an nFET. 
     
     
         7 . The integrated circuit of  claim 2 , wherein the second semiconductor material is SiGe doped with a second dopant such that the second finFET is a pFET. 
     
     
         8 . The integrated circuit of  claim 1 , wherein:
 the first finFET is part of a first set of two or more adjacent, parallel instances of the first finFET;   the second finFET is part of a second set of two or more adjacent, parallel instances of the second finFET;   the third finFET is part of a third set of two or more adjacent, parallel instances of the third finFET; and   the finFETs of the first, second, and third sets are mutually parallel.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the fins of the first set are spaced laterally at a uniform spacing interval. 
     
     
         10 . The integrated circuit of  claim 9 , wherein the fins of the second set are spaced laterally at a uniform spacing interval. 
     
     
         11 . The integrated circuit of  claim 8 , wherein each finFET of the first set is a single-fin FET having its own gate structure. 
     
     
         12 . The integrated circuit of  claim 8 , wherein the two or more finFETs of the first set are part of a single multi-fin FET having a single gate structure. 
     
     
         13 . The integrated circuit of  claim 1 , further comprising insulating material between the first, second, and third fins. 
     
     
         14 . The integrated circuit of  claim 13 , wherein the insulating material extends higher than the lower portions of the first, second, and third fins and lower than the upper portions of the first, second, and third fins. 
     
     
         15 . The integrated circuit of  claim 1 , wherein:
 the lower portions of the first, second, and third fins are of approximately same height above the substrate; and   the upper portions of the first, second, and third fins are of approximately same height above the substrate.   
     
     
         16 . The structure of  claim 1 , wherein the first, second, and third fins are of approximately same width. 
     
     
         17 . The integrated circuit of  claim 1 , wherein, in at least one of the first, second, and third finFETs, the upper portion of the corresponding fin is epitaxially grown on the lower portion. 
     
     
         18 . The integrated circuit of  claim 17 , wherein, in each of the first, second, and third finFETs, the upper portion of the corresponding fin is epitaxially grown on the lower portion. 
     
     
         19 . The integrated circuit of  claim 1 , wherein each of the first, second, and third finFETs is a single-fin FET having its own gate structure. 
     
     
         20 . The integrated circuit of  claim 1 , wherein the first, second, and third finFETs are part of a single multi-fin FET having a single gate structure. 
     
     
         21 . The integrated circuit of  claim 1 , wherein the upper portions of the first, second, and third fins have a thickness between 5 nm and 50 nm. 
     
     
         22 . The integrated circuit of  claim 21 , wherein the upper portions of the first, second, and third fins have a thickness between 20 nm and 40 nm. 
     
     
         23 . The integrated circuit of  claim 22 , wherein the upper portions of the first, second, and third fins have a thickness of approximately 30 nm. 
     
     
         24 . The integrated circuit of  claim 1 , wherein the first, second, and third fins have a width between 5 nm and 100 nm. 
     
     
         25 . The integrated circuit of  claim 24 , wherein the first, second, and third fins have a width between 5 nm and 50 nm.