Semiconductor device under bump structure and method therefor

Abstract

A method of manufacturing a semiconductor device is provided. The method includes depositing a non-conductive layer over a semiconductor die. An opening is formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die. A cavity is in the non-conductive layer with a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer. A conductive layer is formed over the non-conductive layer and the portion of the bond pad. The conductive layer is configured to interconnect the bond pad with a conductive layer portion over the cavity.

What is claimed is: 
     
         1 - 9 . (canceled) 
     
     
         10 . A semiconductor device comprising:
 a semiconductor die having a passivation layer, an opening in the passivation layer exposing a portion of a top surface of a bond pad;   a non-conductive layer formed over the semiconductor die;   an opening formed through the non-conductive layer exposing the portion of the top surface of the bond pad;   a cavity formed in a top surface of the non-conductive layer, a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer; and   a conductive layer formed over the non-conductive layer and the portion of the top surface of the bond pad, the conductive layer patterned and configured to interconnect the bond pad with a conductive layer portion over the cavity.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the conductive layer portion over the cavity is configured for attachment of a ball connector. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the non-conductive layer is characterized as a layer comprising a photosensitive solder mask material or a molding compound material layer. 
     
     
         13 . The semiconductor device of  claim 10 , further comprising a protectant layer formed over at least exposed portions of the conductive layer. 
     
     
         14 . The semiconductor device of  claim 10 , further comprising a seed layer formed on the non-conductive layer and the exposed surface of the bond pad, the conductive layer plated on the seed layer. 
     
     
         15 . The semiconductor device of  claim 10 , wherein the cavity formed in the top surface of the non-conductive layer is located over the semiconductor die. 
     
     
         16 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a semiconductor die having a passivation layer, an opening in the passivation layer exposing a portion of a top surface of a bond pad;   a non-conductive layer formed over the semiconductor die;   an opening formed through the non-conductive layer exposing the portion of the top surface of the bond pad;   a cavity formed in a top surface of the non-conductive layer, a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer; and   a conductive layer formed over the non-conductive layer and the portion of the top surface of the bond pad, the conductive layer configured to interconnect the bond pad with a conductive layer portion over the cavity, the conductive layer conformal with the cavity to form a recess in the conductive layer portion within sidewalls of the cavity.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the recess in the conductive layer portion over the cavity is configured for attachment of a ball connector, and wherein the ball connector occupies the recess in the conductive layer portion. 
     
     
         23 . The semiconductor device of  claim 21 , wherein the non-conductive layer is characterized as a layer comprising a photosensitive solder mask material or a molding compound material layer. 
     
     
         24 . The semiconductor device of  claim 21 , further comprising a protectant layer formed over at least exposed portions of the conductive layer. 
     
     
         25 . The semiconductor device of  claim 21 , further comprising a seed layer formed on the non-conductive layer and the exposed surface of the bond pad, the conductive layer plated on the seed layer. 
     
     
         26 . The semiconductor device of  claim 21 , wherein the cavity formed in the top surface of the non-conductive layer is located over the semiconductor die. 
     
     
         27 . The semiconductor device of  claim 21 , wherein the cavity formed in the top surface of the non-conductive layer is located over a package encapsulant. 
     
     
         28 . The semiconductor device of  claim 21 , wherein the non-conductive layer is formed directly on the passivation layer of the semiconductor die. 
     
     
         29 . A semiconductor device comprising:
 a semiconductor die having a passivation layer, an opening in the passivation layer exposing a portion of a top surface of a bond pad;   a non-conductive layer formed over the semiconductor die, an opening formed through the non-conductive layer exposing the portion of the top surface of the bond pad;   a cavity formed in a top surface of the non-conductive layer, a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer; and   a conductive layer formed over the non-conductive layer and the portion of the top surface of the bond pad, the conductive layer patterned and configured to interconnect the bond pad with a conductive layer portion over the cavity, the conductive layer conformal with the cavity to form a recess in the conductive layer portion within sidewalls of the cavity.   
     
     
         30 . The semiconductor device of  claim 29 , wherein the recess in the conductive layer portion over the cavity is configured for attachment of a ball connector, and wherein the ball connector occupies the recess in the conductive layer portion. 
     
     
         31 . The semiconductor device of  claim 29 , wherein the non-conductive layer is characterized as a layer comprising a photosensitive solder mask material or a molding compound material layer. 
     
     
         32 . The semiconductor device of  claim 29 , further comprising a protectant layer formed over at least exposed portions of the conductive layer. 
     
     
         33 . The semiconductor device of  claim 29 , further comprising a seed layer formed on the non-conductive layer and the exposed surface of the bond pad, the conductive layer plated on the seed layer. 
     
     
         34 . The semiconductor device of  claim 29 , wherein the cavity formed in the top surface of the non-conductive layer is located over the semiconductor die.