Methods for reducing scratch defects in chemical mechanical planarization

Abstract

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

What is claimed is: 
     
         1 . A method, comprising:
 receiving a workpiece comprising:
 a substrate, 
 an active region disposed over the substrate and extending lengthwise along a first direction, and 
 a dummy gate structure disposed over the active region and the substrate and extending along a second direction perpendicular to the first direction; 
   depositing an etch stop layer (ESL) over the workpiece;   depositing a first dielectric layer over the ESL;   hardening the first dielectric layer, resulting in a hardened portion of the first dielectric layer;   after the hardening of the first dielectric layer, depositing a second dielectric layer over the hardened portion of the first dielectric layer, wherein the second dielectric layer has a second hardness higher than the first hardness; and   performing a chemical mechanical planarization (CMP) process to both the first dielectric layer and the second dielectric layer to completely remove the second dielectric layer and partially remove the hardened portion of the first dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the dummy gate structure comprises:
 an oxide layer disposed on the active region;   a dummy electrode layer disposed over the oxide layer;   a hard mask layer over the dummy electrode layer; and   a capping layer over the hard mask layer.   
     
     
         3 . The method of  claim 2 , wherein, after the depositing of the ESL, the ESL is in direct contact with the oxide layer, the dummy electrode layer, the hard mask layer, and the capping layer. 
     
     
         4 . The method of  claim 2 ,
 wherein the dummy electrode layer comprises polysilicon,   wherein the hard mask layer comprises silicon nitride,   wherein the capping layer comprises silicon oxide.   
     
     
         5 . The method of  claim 1 , wherein the hardening of the first dielectric layer comprises:
 treating the first dielectric layer with an oxidizer; and   after the treating of the first dielectric layer, treating the first dielectric layer with deionized water (DIW).   
     
     
         6 . The method of  claim 5 , wherein the treating of the first dielectric layer is performed at a temperature ranging from 15° C. to 90° C. and the oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the oxidizer ranges from 0.005% to 0.1%. 
     
     
         7 . The method of  claim 5 , wherein the treating of the first dielectric layer is performed at room temperature. 
     
     
         8 . The method of  claim 5 , wherein the oxidizer is aqueous. 
     
     
         9 . The method of  claim 1 , wherein the hardened portion of the first dielectric layer extends below a top surface of the dummy gate structure. 
     
     
         10 . A method, comprising:
 receiving a workpiece comprising:
 a substrate, 
 a fin structure rising from the substrate and extending lengthwise along a first direction, and 
 a dummy gate structure disposed over the fin structure and the substrate and extending lengthwise along a second direction; 
   depositing a first dielectric layer over the fin structure and the dummy gate structure, the first dielectric layer comprising silicon and oxygen and having a first content of silicon-oxygen bonds;   treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, the treated portion of the first dielectric layer having a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds;   depositing a second dielectric layer over the treated portion of the first dielectric layer;   performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the treated portion of the first dielectric layer; and   replacing the dummy gate structure with a metal gate structure.   
     
     
         11 . The method of  claim 10 , wherein the dummy gate structure comprises:
 an oxide layer disposed on the fin structure;   a dummy electrode layer disposed over the oxide layer;   a hard mask layer over the dummy electrode layer; and   a capping layer over the hard mask layer.   
     
     
         12 . The method of  claim 10 , wherein the metal gate structure comprises:
 an interfacial layer disposed on the fin structure;   a high-k gate dielectric layer over the interfacial layer;   a work function metal layer over the high-k gate dielectric layer; and   a metal fill layer over the work function metal layer.   
     
     
         13 . The method of  claim 10 , wherein the aqueous oxidizer is deionized water (DIW) or dilute hydrofluoric acid (DHF). 
     
     
         14 . A method of forming a semiconductor device, the method comprising:
 providing a substrate and dummy gate structures over the substrate, the dummy gate structures being interposed by trenches;   depositing a first dielectric layer over the dummy gate structures and filling the trenches, the first dielectric layer containing silicon and oxygen;   hardening the first dielectric layer with an aqueous oxidizer, resulting in a hardened portion of the first dielectric layer;   depositing a second dielectric layer over the hardened portion; and   performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the hardened portion of the first dielectric layer.   
     
     
         15 . The method of  claim 14 , wherein the aqueous oxidizer is one of: deionized water (DIW) and dilute hydrofluoric acid (DHF). 
     
     
         16 . The method of  claim 14 , wherein the first dielectric layer has a first hardness before the hardening of the first dielectric layer, the hardened portion has a second hardness greater than the first hardness, and the second dielectric layer has a third hardness greater than the second hardness. 
     
     
         17 . The method of  claim 14 , wherein the hardening the first dielectric layer with an aqueous oxidizer comprises a first treating process with deionized water (DIW) and a second treating process with dilute hydrofluoric acid (DHF). 
     
     
         18 . The method of  claim 17 , wherein a concentration of hydrofluoric acid in the DHF ranges from 0.005% to 0.1%. 
     
     
         19 . The method of  claim 14 , further comprising annealing the first dielectric layer at a temperature between about 300° C. and about 1200° C. 
     
     
         20 . The method of  claim 14 , wherein each of the dummy gate structures comprises an oxide layer, a gate electrode layer over the oxide layer, and a hard mask layer over the gate electrode layer.