Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate defining a pixel area; a trench fill structure formed in the substrate in the pixel area; a buffer dielectric layer formed over a surface of the substrate in the pixel area, the buffer dielectric layer defining a first opening, which at least exposes a portion of the substrate surrounding the trench fill structure; and a metal grid layer formed on the buffer dielectric layer, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate, thus allowing optimization or amelioration of the semiconductor device's electrical performance.

What is claimed is: 
     
         1 . A semiconductor device, comprising
 a substrate defining a pixel area;   a trench fill structure formed in the substrate in the pixel area;   a buffer dielectric layer formed over a surface of the substrate in the pixel area, the buffer dielectric layer defining a first opening, which at least exposes a portion of the substrate surrounding the trench fill structure; and   a metal grid layer formed on the buffer dielectric layer, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein both a portion of the substrate surrounding a top edge of the trench fill structure and an entire top surface of the trench fill structure are exposed in the first opening, the metal grid layer being in direct contact with and electrically connected to both the portion of the substrate surrounding the top edge of the trench fill structure and the entire top surface of the trench fill structure. 
     
     
         3 . The semiconductor device of  claim 1 , wherein part of the top surface of the trench fill structure is exposed in the first opening, the metal grid layer being in direct contact with and electrically connected to the part of the top surface of the trench fill structure. 
     
     
         4 . The semiconductor device of  claim 1 , wherein only a portion of the substrate surrounding a top edge of the trench fill structure is exposed in the first opening, the metal grid layer being in direct contact with and electrically connected to the portion of the substrate surrounding the top edge of the trench fill structure. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the metal grid layer is in direct contact with and electrically connected to the exposed portion of the substrate to apply a bias voltage to a backside of the substrate. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the trench fill structure comprises an isolation oxide layer covering a surface of the trench in the substrate and a filler material that fills the trench, the isolation oxide layer at least located between a sidewall of the filler material and the substrate. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the substrate further defines a pad area lateral to the pixel area, and wherein a metal interconnect structure and a plug structure above the metal interconnect structure are formed in the substrate in the pad area, the plug structure electrically connected at a bottom thereof to the metal interconnect structure. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the trench fill structure comprises a first conductive metal layer in a trench formed in the pixel area, and the plug structure comprises: an isolation oxide layer covering a sidewall of a through-hole in which a top surface of the metal interconnect structure is partially exposed; and a first conductive metal layer that fills the through-hole. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the buffer dielectric layer also covers a surface of the substrate in the pad area and defines a second opening in which a top surface of the plug structure is partially exposed, and wherein a pad structure is formed on the buffer dielectric layer in the pad area and completely fills the second opening so as to be electrically connected to the exposed portion of the top surface of the plug structure.