US2023420547A1PendingUtilityA1

Vertical gallium nitride based fets with regrown source contacts

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Assignee: NEXGEN POWER SYSTEMS INCPriority: Mar 27, 2020Filed: Jun 23, 2023Published: Dec 28, 2023
Est. expiryMar 27, 2040(~13.7 yrs left)· nominal 20-yr term from priority
Inventors:Clifford DrowleyAndrew P. EdwardsSubhash Srinivas PidaparthiShahin Sharifzadeh
H10D 62/8503H10D 62/151H10D 30/62H10D 30/021H10D 30/83H10D 30/051H10D 30/015H10D 64/64H10D 30/675H10D 30/6738H10D 64/62H10D 62/85H10D 62/60H10D 62/343H10D 62/124H10D 62/328H10D 62/161H10D 62/149H10D 62/117H10D 62/405H10D 84/834H10D 84/0158H10D 84/016H10D 84/038H10D 30/0243H10D 30/472H10D 84/013H01L 29/6681H01L 29/66522H01L 29/785H01L 29/0847H01L 29/2003
68
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Claims

Abstract

A transistor includes a III-nitride substrate, a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type, and a plurality of III-nitride fins on the first III-nitride layer, wherein each of the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type. The transistor also includes a III-nitride gate layer having a second conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface, and a regrown III-nitride source contact portion coupled to each of the plurality of III-nitride fins, wherein the regrown III-nitride source contact portion is characterized by the first conductivity type.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A transistor comprising:
 a III-nitride substrate;   a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type;   a plurality of III-nitride fins on the first III-nitride layer, wherein each of the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type;   a III-nitride gate layer having a second conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; and   a regrown III-nitride source contact portion coupled to each of the plurality of III-nitride fins, wherein the regrown III-nitride source contact portion is characterized by the first conductivity type.   
     
     
         2 . The transistor of  claim 1  wherein the III-nitride substrate comprises an n-GaN substrate. 
     
     
         3 . The transistor of  claim 1  wherein sidewalls of each of the plurality of III-nitride fins are aligned with an m-plane and the fin surface is aligned with a c-plane. 
     
     
         4 . The transistor of  claim 1  wherein the regrown III-nitride source contact portion is characterized by a self-limiting growth process on top of each of the plurality of III-nitride fins. 
     
     
         5 . The transistor of  claim 1  wherein the regrown III-nitride source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view. 
     
     
         6 . The transistor of  claim 1  wherein a width of the regrown III-nitride source contact portion is at least three times of that of a width of each of the plurality of III-nitride fins. 
     
     
         7 . The transistor of  claim 1 , further comprising a undoped III-nitride cap layer coupled to the III-nitride gate layer. 
     
     
         8 . The transistor of  claim 1  wherein the first III-nitride layer and the plurality of III-nitride fins comprise n-GaN epitaxial material. 
     
     
         9 . The transistor of  claim 1  wherein the first III-nitride layer is characterized by a first dopant concentration and the plurality of III-nitride fins is characterized by a second dopant concentration. 
     
     
         10 . The transistor of  claim 9  wherein the second dopant concentration is higher than the first dopant concentration. 
     
     
         11 . The transistor of  claim 9  wherein the regrown III-nitride source contact portion is characterized by a third dopant concentration that is different from the second dopant concentration. 
     
     
         12 . The transistor of  claim 1  wherein the III-nitride substrate comprises an n-GaN substrate, the first III-nitride layer and the plurality of III-nitride fins comprise n-GaN epitaxial layers, and the III-nitride gate layer comprises a p-GaN epitaxial layer. 
     
     
         13 . The transistor of  claim 1  further comprising a graded III-nitride layer disposed between the first III-nitride layer and the plurality of III-nitride fins, wherein a graded conductivity of the graded III-nitride layer varies as a function of distance from the first III-nitride layer. 
     
     
         14 . The transistor of  claim 1 , further comprising a source contact structure coupled to the regrown III-nitride source contact portion. 
     
     
         15 . The transistor of  claim 14  wherein the source contact structure comprises Ti, Al, and Mo positioned from bottom to top on the regrown III-nitride source contact portion. 
     
     
         16 . The transistor of  claim 14  wherein the source contact structure comprises Ti, TiN, and Al positioned from bottom to top on the regrown III-nitride source contact portion. 
     
     
         17 . The transistor of  claim 1  further comprising a gate contact structure disposed on the III-nitride gate layer.

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