Semiconductor chip, semiconductor device, and semiconductor package including the same

Abstract

A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.

1 . A semiconductor device comprising:
 a first semiconductor chip, the first semiconductor chip comprising:   a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view;   a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer;   a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode;   a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and   a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode,   wherein the first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first dummy pattern comprises a plurality of dummy patterns disposed on the same plane, and the dummy patterns comprise a plurality of line patterns disposed adjacent to the four sides of the quadrangle shape of the first semiconductor substrate from the plan view and spaced apart from each other. 
     
     
         3 - 7 . (canceled) 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a second semiconductor chip mounted on the first semiconductor chip; and   a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip,   wherein the second semiconductor chip comprises: a second semiconductor substrate having a third surface and a fourth surface opposite to the first surface, and having a second active layer adjacent to the third surface, the second semiconductor substrate having a quadrangle shape from a plan view; a second through electrode penetrating at least a portion of the second semiconductor substrate and connected to the second active layer; a fourth chip connection pad on the fourth surface of the second semiconductor substrate and connected to the second through electrode; a second dummy pattern positioned outside the fourth chip connection pad on the fourth surface of the second semiconductor substrate from the plan view, the second dummy pattern comprising a line pattern extending horizontally along the fourth surface of the second semiconductor substrate; a third chip connection pad on the third surface of the second semiconductor substrate and connected to the second through electrode; and a first connection terminal attached to the third chip connection pad to connect the third chip connection pad to the second chip connection pad, wherein the second dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the second semiconductor substrate from the plan view,   wherein the first adhesive layer surrounds the second chip connection pad, the third chip connection pad, the first connection terminal, and the first dummy pattern.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first dummy pattern comprises a plurality of first dummy patterns disposed on a first plane, and the first dummy patterns comprise a plurality of first line patterns arranged adjacent to and spaced apart from four sides of a quadrangle shape of the first semiconductor substrate from the plan view, and
 wherein the second dummy pattern comprises a plurality of second dummy patterns disposed on a second plane, and the second dummy patterns comprise a plurality of second line patterns disposed adjacent to and spaced apart from the four sides of the quadrangle shape of the second semiconductor substrate from the plan view.   
     
     
         10 . The semiconductor device of  claim 8 , wherein a height of the first dummy pattern above the second surface of the first semiconductor substrate is greater than a height of the second chip connection pad above the second surface of the first semiconductor substrate, and a height of the second dummy pattern above the fourth surface of the second semiconductor substrate is greater than a height of the fourth chip connection pad above the fourth surface of the second semiconductor substrate. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the first dummy pattern has an integral structure with the first semiconductor substrate, and the second dummy pattern has an integral structure with the second semiconductor substrate. 
     
     
         12 . The semiconductor device of  claim 8 , wherein the first adhesive layer protrudes from opposite side surfaces of each of the first semiconductor substrate and the second semiconductor substrate. 
     
     
         13 . The semiconductor device of  claim 8 , wherein the first adhesive layer contacts with opposite side surfaces of each of the first semiconductor substrate and the second semiconductor substrate. 
     
     
         14 . The semiconductor device of  claim 8 , wherein the first dummy pattern contacts both the second surface of the first semiconductor substrate and the third surface of the second semiconductor substrate. 
     
     
         15 - 16 . (canceled) 
     
     
         17 . The semiconductor device of  claim 8 , further comprising:
 a base chip, the first semiconductor chip being mounted on the base chip;   a base adhesive layer disposed between the base chip and the first semiconductor chip; and   an encapsulation layer surrounding the first semiconductor chip, the second semiconductor chip, the base adhesive layer, and the first adhesive layer on the base chip;   wherein the base chip comprises: a base substrate having a base lower surface and a base upper surface opposite the base lower surface; an external connection pad disposed on the base lower surface; an external connection terminal connected to the external connection pad; and an internal connection pad disposed on the base upper surface of the base substrate,   wherein the first semiconductor chip comprises: a second connection terminal connected to the first chip connection pad and the internal connection pad,   wherein the base adhesive layer surrounds the first chip connection pad and the second connection terminal, and   wherein the semiconductor device is a semiconductor package.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the first dummy pattern comprises a plurality of first dummy patterns disposed on a first plane, and the first dummy patterns comprise a plurality of first line patterns arranged adjacent to and spaced apart from four sides of a quadrangle shape of the first semiconductor substrate from the plan view, and
 wherein the second dummy pattern comprises a plurality of second dummy patterns disposed on a second plane, and the second dummy patterns comprise a plurality of second line patterns disposed adjacent to and spaced apart from the four sides of the quadrangle shape of the second semiconductor substrate from the plan view.   
     
     
         19 . The semiconductor device of  claim 17 , wherein the first adhesive layer contacts opposite side surfaces of the first semiconductor substrate and the second semiconductor substrate, and the first adhesive layer is not exposed to the outside of the semiconductor package by the encapsulation layer. 
     
     
         20 . The semiconductor package of  claim 17 , wherein a third semiconductor chip is further disposed on the second semiconductor chip with a second adhesive layer therebetween, and the encapsulation layer surrounds the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the base adhesive layer, and the first adhesive layer. 
     
     
         21 . A semiconductor device comprising:
 a first semiconductor chip, the first semiconductor chip comprising:   a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view;   a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate and connected to the first active layer;   a plurality of second chip connection pads on the second surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes;   a plurality of protruding line patterns positioned outside the plurality of second chip connection pads on the second surface of the first semiconductor substrate from the plan view, each line pattern of the plurality of protruding line patterns extending horizontally along the second surface of the first semiconductor substrate; and   a plurality of first chip connection pads on the first surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes,   wherein the plurality of protruding line patterns are disposed adjacent to respective sides of the quadrangle shape of the first semiconductor substrate from the plan view.   
     
     
         22 . The semiconductor device of  claim 21 , wherein each protruding line pattern of the plurality of protruding line patterns has a bar shape extending adjacent to a respective side of the quadrangle shape along only a portion of the respective side. 
     
     
         23 . The semiconductor device of  claim 22 , wherein the plurality of protruding line patterns are formed of the same material as the first semiconductor substrate or of a different, insulating material. 
     
     
         24 . The semiconductor device of  claim 21 , further comprising:
 a second semiconductor chip disposed on the second surface of the first semiconductor chip; and   an adhesive layer formed between the second semiconductor chip and the second surface of the first semiconductor chip;   wherein the adhesive layer surrounds and contacts the plurality of protruding line patterns.   
     
     
         25 . The semiconductor device of  claim 24 , wherein the adhesive layer extends horizontally beyond side surfaces of the first semiconductor chip and the second semiconductor chip. 
     
     
         26 . The semiconductor device of  claim 25 , further comprising:
 an encapsulation layer formed to surround the side surfaces of the first and second semiconductor chips and side surfaces of the adhesive layer.   
     
     
         27 . The semiconductor device of  claim 24 , wherein plurality of protruding line patterns are dam structures that control the flow of an adhesive material that forms the adhesive layer.