Trench shielded transistor

Abstract

An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 first and second trenches in a semiconductor substrate;   a semiconductor mesa between the first and second trenches;   a source region having a first conductivity type and a body region having an opposite second conductivity type within the semiconductor mesa,   a trench shield within the first trench;   a gate electrode over the trench shield between first and second sidewalls of the first trench;   a gate dielectric on a sidewall of the first trench between the gate electrode and the body region;   a pre-metal dielectric (PMD) layer over the gate electrode;   a gate contact through the PMD layer that touches the gate electrode between the first and second sidewalls; and   a trench shield contact through the PMD layer that touches the trench shield between the first and second sidewalls.   
     
     
         2 . The integrated circuit of  claim 1  wherein the gate contact and the trench shield contact have a same depth below a top surface of the semiconductor substrate. 
     
     
         3 . The integrated circuit of  claim 1  further including a source contact electrically contacting the source region, the source contact and the gate contact having a same depth below a top surface of the semiconductor substrate. 
     
     
         4 . The integrated circuit of  claim 1  further comprising a source contact ohmically contacting the source region, wherein tops of the gate contact, the trench shield contact and the source contact are coplanar. 
     
     
         5 . The integrated circuit of  claim 1  wherein the PMD layer comprises a planarized dielectric layer. 
     
     
         6 . The integrated circuit of  claim 5  and further including interconnections in a metal layer over the planarized dielectric layer, the interconnections having top surfaces that are coplanar. 
     
     
         7 . The integrated circuit of  claim 1  and further including:
 a first trench shield contact electrically contacting the trench shield between the first and second sidewalls. 
 
     
     
         8 . The integrated circuit of  claim 7  wherein the trench shield has a first portion with a top surface at a first depth below a top surface of the semiconductor substrate, and has a second portion having a top surface at a second depth below the top surface, wherein the first depth is greater than the second depth and the trench shield contact touches the trench shield along the second portion of the trench shield. 
     
     
         9 . The integrated circuit of  claim 1  wherein the gate contact and the trench shield contact have a same depth below a surface of a pre-metal dielectric (PMD) layer over the semiconductor substrate. 
     
     
         10 . A semiconductor device, comprising:
 a trench located in a semiconductor layer;   a polysilicon gate electrode within the trench and having a first portion in contact with a pre-metal dielectric (PMD) layer;   a polysilicon shield within the trench and having a first portion in contact with the PMD layer and a second section spaced apart from the PMD layer by the gate electrode;   a gate contact extending from a top surface of the PMD layer to the gate electrode; and   a trench shield contact extending from the top surface of the PMD layer to the first portion of the polysilicon shield.   
     
     
         11 . The semiconductor device of  claim 10  wherein a top surface of the gate contact is coplanar with a top surface of the shield contact. 
     
     
         12 . The semiconductor device of  claim 10  wherein the gate contact is electrically connected to a first metal layer over the PMD layer, and the shield contact is electrically connected to a different second metal layer over the PMD layer, the first metal layer being coplanar with the second metal layer. 
     
     
         13 . The semiconductor device of  claim 10  further comprising a source contact extending from the top surface of the PMD layer to the semiconductor layer adjacent the trench, wherein a top surface of the source contact is coplanar with top surfaces of the gate contact and the shield contact. 
     
     
         14 . A method of forming an integrated circuit, comprising:
 forming a trench in a semiconductor substrate, the trench having first and second trench sidewalls;   forming a first dielectric layer along the first and second trench sidewalls;   forming a polysilicon element between the first and second trench sidewalls, the polysilicon element spaced apart from the first trench sidewall and the second trench sidewall by the first dielectric layer;   partially removing the polysilicon element along a portion of the trench thereby forming a trench shield;   forming a gate conductor within the trench portion and spaced apart from the trench shield by a lateral insulator; and   forming a trench shield contact that lands on the trench shield and a gate contact that lands on the gate conductor, the trench shield contact and gate contact extending through a pre-metal dielectric (PMD) layer over the trench.   
     
     
         15 . The method of  claim 14  and further including forming a source region in the semiconductor substrate and adjacent the trench. 
     
     
         16 . The method of  claim 14  further comprising planarizing the PMD layer before forming the shield contact and the gate contact. 
     
     
         17 . The method of  claim 14  wherein the shield contact and the gate contact extend a same distance between a top surface of the PMD layer and a bottom of the trench. 
     
     
         18 . The method of  claim 14  and further including:
 forming a source region in the semiconductor substrate and adjacent the trench; and 
 forming source contact that lands in the source region and extends through the PMD layer, 
 wherein top surfaces of the gate contact, the shield contact and the source contact are coplanar. 
 
     
     
         19 . The method of  claim 18 , wherein the gate contact, the shield contact and the source contact are formed concurrently.