Memory device with tapered bit line contact and method for preparing the same

Abstract

A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

What is claimed is: 
     
         1 . A method for preparing a memory device, comprising:
 forming a doped region in a semiconductor substrate;   forming a word line across the doped region such that a first source/drain region and a second source/drain region are formed in the doped region and on opposite sides of the word line;   forming a dielectric cap layer covering the word line, the first source/drain region and the second source/drain region;   forming a first opening penetrating through the dielectric cap layer to expose the first source/drain region, wherein the first opening has a tapered profile along a direction from a top surface of the dielectric cap layer towards the first source/drain region;   forming a bit line contact in the first opening;   forming a second opening penetrating through the dielectric cap layer to expose the second source/drain region; and   forming a capacitor contact in the second opening.   
     
     
         2 . The method for preparing a memory device of  claim 1 , wherein a top width of the first opening is greater than a bottom width of the first opening. 
     
     
         3 . The method for preparing a memory device of  claim 1 , wherein the word line comprises a gate electrode and a gate dielectric layer surrounding the gate electrode, and the gate dielectric layer is exposed by the first opening. 
     
     
         4 . The method for preparing a memory device of  claim 1 , wherein the forming the first opening comprises:
 performing a first etching process on the dielectric cap layer using a first etchant gas including CH 4 /CHF 3 .   
     
     
         5 . The method for preparing a memory device of  claim 4 , wherein the forming the first opening comprises:
 performing a second etching process on the dielectric cap layer using a second etchant gas including CH 4 /CH 2 F 2  after the first etching process is performed.   
     
     
         6 . The method for preparing a memory device of  claim 1 , further comprising:
 depositing a spacer layer over the dielectric cap layer after the first opening is formed; and   partially removing the spacer layer to expose the first source/drain region, thereby forming a bit line contact spacer covering a sidewall of the first opening.   
     
     
         7 . The method for preparing a memory device of  claim 6 , wherein a remaining portion of the first opening is filled by the bit line contact after the bit line contact spacer is formed. 
     
     
         8 . The method for preparing a memory device of  claim 1 , further comprising:
 forming a bit line over the bit line contact, wherein the bit line contact is tapered from the bit line to the first source/drain region.   
     
     
         9 . The method for preparing a memory device of  claim 8 , further comprising:
 forming a bit line spacer covering a sidewall of the bit line.   
     
     
         10 . The method for preparing a memory device of  claim 9 , further comprising:
 forming a dielectric layer over the dielectric cap layer, wherein the bit line and the bit line spacer are covered by the dielectric layer; and   forming the second opening penetrating through the dielectric layer and the dielectric cap layer to expose the second source/drain region.