Titanium nitride gapfill processes for semiconductor devices

Abstract

One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as finFETs, GAAs, and the like, without creating a seam. The methods include selective deposition processes using blocking compounds in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

What is claimed is: 
     
         1 . A method of forming a semiconductor device, the method comprising:
 conformally depositing a first titanium nitride (TiN) layer on a semiconductor structure formed on a top surface of a semiconductor substrate, the semiconductor structure comprising a plurality of nanosheets, each of the plurality of nanosheets separated by a trench;   exposing the plurality of nanosheets having the first TiN layer thereon to a blocking compound to form a blocking layer on a portion of the first TiN layer;   forming a second titanium nitride (TiN) layer to fill a portion of the trench, the second TiN layer growing from within the trench;   removing the blocking layer; and   forming a third titanium nitride (TiN) layer, the first TiN layer, the second TiN layer, and the third TiN layer combining to fill the trench with a titanium nitride (TiN) gapfill material that is substantially free of seams and voids.   
     
     
         2 . The method of  claim 1 , wherein the semiconductor structure is formed by patterning a superlattice structure on the top surface of the semiconductor substrate, the superlattice structure comprising a plurality of nanosheet channel layers and a corresponding plurality of nanosheet release layers alternatingly arranged in a plurality of stacked pairs to remove the plurality of nanosheet release layers. 
     
     
         3 . The method of  claim 2 , wherein the plurality of nanosheet channel layers comprise silicon germanium (SiGe) and the plurality of nanosheet release layers comprise silicon (Si). 
     
     
         4 . The method of  claim 2 , wherein the plurality of nanosheet channel layers comprise silicon (Si) and the plurality of nanosheet release layers comprise silicon germanium (SiGe). 
     
     
         5 . The method of  claim 1 , wherein forming one or more of the first TiN layer, the second TiN layer, or the third TiN layer comprises exposing the semiconductor structure to a titanium-containing precursor and a nitrogen-containing precursor. 
     
     
         6 . The method of  claim 5 , wherein the titanium-containing precursor comprises titanium tetrachloride (TiCl 4 ) and the nitrogen-containing precursor comprises ammonia (NH 3 ). 
     
     
         7 . The method of  claim 1 , wherein the blocking compound comprises a formula of R 1 —C≡C—R 2 , where each of R 1  and R 2  are independently hydrogen (H) or an alkyl chain, a formula of H—C≡C—R 3 , where R 3  is an alkyl chain, a formula of R—SiH 3 , where R is an alkyl chain, a formula of R—SiCl 3 , where R is an alkyl chain, or a formula of R—SH, where R is an alkyl chain. 
     
     
         8 . The method of  claim 7 , wherein R 1  and R 2  are the same. 
     
     
         9 . The method of  claim 1 , wherein forming one or more of the first TiN layer, the second TiN layer, or the third TiN layer and forming the blocking layer occurs in the same semiconductor processing chamber. 
     
     
         10 . The method of  claim 9 , wherein the semiconductor processing chamber is an atomic layer deposition (ALD) chamber. 
     
     
         11 . The method of  claim 1 , wherein the semiconductor device is a gate-all-around (GAA) transistor. 
     
     
         12 . A method of forming a gate-all-around (GAA) transistor, the method comprising:
 forming a superlattice structure on a top surface of a substrate, the superlattice structure comprising a plurality of nanosheet channel layers and a corresponding plurality of nanosheet release layers alternatingly arranged in a plurality of stacked pairs;   patterning the superlattice structure to remove the plurality of nanosheet release layers and form a semiconductor structure comprising a plurality of nanosheets, each of the plurality of nanosheets separated by a trench;   conformally depositing a first titanium nitride (TiN) layer on the plurality of nanosheets;   exposing the plurality of nanosheets having the first TiN layer thereon to a blocking compound to form a blocking layer on a portion of the first TiN layer;   forming a second titanium nitride (TiN) layer to fill a portion of the trench, the second TiN layer growing from within the trench;   removing the blocking layer; and   forming a third titanium nitride (TiN) layer, the first TiN layer, the second TiN layer, and the third TiN layer combining to fill the trench with a titanium nitride (TiN) gapfill material that is substantially free of seams and voids.   
     
     
         13 . The method of  claim 12 , wherein the plurality of nanosheet channel layers comprise silicon (Si) and the plurality of nanosheet release layers comprise silicon germanium (SiGe). 
     
     
         14 . The method of  claim 12 , wherein the plurality of nanosheet channel layers comprise silicon germanium (SiGe) and the plurality of nanosheet release layers comprise silicon (Si). 
     
     
         15 . The method of  claim 12 , wherein forming one or more of the first TiN layer, the second TiN layer, or the third TiN layer comprises exposing the semiconductor structure to a titanium-containing precursor and a nitrogen-containing precursor. 
     
     
         16 . The method of  claim 15 , wherein the titanium-containing precursor comprises titanium tetrachloride (TiCl 4 ) and the nitrogen-containing precursor comprises ammonia (NH 3 ). 
     
     
         17 . The method of  claim 12 , wherein the blocking compound comprises a formula of R 1 —C≡C—R 2 , where each of R 1  and R 2  are independently hydrogen (H) or an alkyl chain, a formula of H—C≡C—R 3 , where R 3  is an alkyl chain, a formula of R—SiH 3 , where R is an alkyl chain, a formula of R—SiCl 3 , where R is an alkyl chain, or a formula of R—SH, where R is an alkyl chain. 
     
     
         18 . The method of  claim 17 , where R 1  and R 2  are the same. 
     
     
         19 . The method of  claim 12 , wherein forming one or more of the first TiN layer, the second TiN layer, or the third TiN layer and forming the blocking layer occurs in the same semiconductor processing chamber. 
     
     
         20 . A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to:
 conformally deposit a first titanium nitride (TiN) layer on a semiconductor structure formed on a top surface of a semiconductor substrate, the semiconductor structure comprising a plurality of nanosheets, each of the plurality of nanosheets separated by a trench;   expose the plurality of nanosheets having the first TiN layer thereon to a blocking compound to form a blocking layer on a portion of the first TiN layer;   form a second titanium nitride (TiN) layer to fill a portion of the trench, the second TiN layer growing from within the trench;   remove the blocking layer; and   form a third titanium nitride (TiN) layer, the first TiN layer, the second TiN layer, and the third TiN layer combining to fill the trench with a titanium nitride (TiN) gapfill material that is substantially free of seams and voids.