Three dimensional integrated circuit and fabrication thereof

Abstract

A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

What is claimed is: 
     
         1 . A method comprising:
 forming a first transistor on a substrate;   forming a first dielectric layer over the first transistor;   forming a first trench in the first dielectric layer, wherein a bottom of the first trench is at the substrate;   depositing an amorphous semiconductor layer in the first trench and over the first dielectric layer;   crystallizing the amorphous semiconductor layer into a crystalline semiconductor layer; and   forming a second transistor over the crystalline semiconductor layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a second trench in the first dielectric layer, wherein a bottom of the second trench is at the substrate, the first transistor is laterally between the first trench and the second trench, and the amorphous semiconductor layer is further deposited in the second trench.   
     
     
         3 . The method of  claim 1 , further comprising:
 performing a chemical mechanical polish (CMP) process to remove a protrusion from the crystalline semiconductor layer.   
     
     
         4 . The method of  claim 1 , wherein the second transistor has a channel material different from a channel material of the first transistor. 
     
     
         5 . The method of  claim 1 , wherein the first transistor and the second transistor are of different conductivity types. 
     
     
         6 . The method of  claim 1 , wherein the amorphous semiconductor layer is crystallized into the crystalline semiconductor layer by using a laser anneal. 
     
     
         7 . The method of  claim 6 , wherein the laser anneal is performed such that the amorphous semiconductor layer is turned into a liquid phase. 
     
     
         8 . The method of  claim 1 , wherein forming the second transistor comprises:
 forming an epitaxial stack on the crystalline semiconductor layer, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers;   forming a dummy gate structure over the epitaxial stack;   forming gate spacers on opposite sides of the dummy gate structure;   etching portions of the epitaxial stack that are not covered by the dummy gate structure and the gate spacers;   after etching the portions of the epitaxial stack, forming epitaxial source/drain regions on the crystalline semiconductor layer;   removing the dummy gate structure and the first semiconductor layers; and   forming a gate structure surrounding the second semiconductor layers.   
     
     
         9 . The method of  claim 1 , further comprising:
 forming a second dielectric layer over the second transistor;   forming a first via extending in the second dielectric layer to the second transistor; and   forming a second via extending in the first dielectric layer and the second dielectric layer to the first transistor.   
     
     
         10 . The method of  claim 1 , further comprising:
 forming metal vias and metal lines in the first dielectric layer prior to forming the first trench in the first dielectric layer.   
     
     
         11 . A method comprising:
 forming a first transistor on a substrate;   forming a dielectric layer over the substrate;   etching a first trench in the dielectric layer until the substrate is exposed in the first trench;   forming an amorphous semiconductor material in the first trench and over the dielectric layer;   performing an anneal process on the amorphous semiconductor material, the anneal process turning the amorphous semiconductor material into a crystalline semiconductor material;   forming an epitaxial stack on the crystalline semiconductor material, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers; and   replacing the first semiconductor layers with a gate structure.   
     
     
         12 . The method of  claim 11 , wherein the anneal process is a laser anneal. 
     
     
         13 . The method of  claim 12 , wherein the anneal process is performed such that the amorphous semiconductor material is melt into a liquid phase. 
     
     
         14 . The method of  claim 11 , further comprising:
 planarizing the crystalline semiconductor material prior to forming the epitaxial stack.   
     
     
         15 . The method of  claim 11 , further comprising:
 etching a second trench in the dielectric layer until the substrate is exposed in the second trench, wherein the first transistor is laterally between the first trench and the second trench, and the amorphous semiconductor material is further formed in the second trench.   
     
     
         16 . An integrated circuit (IC) structure comprising:
 a first transistor over a substrate;   a second transistor at a different level height than the first transistor;   a first dielectric layer interposing the first transistor and the second transistor;   a first crystalline semiconductor plug extending through the first dielectric layer; and   a crystalline semiconductor lateral portion extending along a top surface of the first dielectric layer, wherein the second transistor is formed over the crystalline semiconductor lateral portion, and the crystalline semiconductor lateral portion is formed of a same material as the first crystalline semiconductor plug.   
     
     
         17 . The IC structure of  claim 16 , wherein the first crystalline semiconductor plug is spaced apart from the crystalline semiconductor lateral portion. 
     
     
         18 . The IC structure of  claim 16 , wherein the first crystalline semiconductor plug is in contact with the substrate. 
     
     
         19 . The IC structure of  claim 16 , further comprising:
 a second crystalline semiconductor plug extending through the first dielectric layer, wherein the first transistor is laterally between the first crystalline semiconductor plug and the second crystalline semiconductor plug.   
     
     
         20 . The IC structure of  claim 16 , further comprising:
 a second dielectric layer over the second transistor; and   metal vias in the second dielectric layer.