Semiconductor Device and Method for Fabricating a Semiconductor Wafer

Abstract

A semiconductor device includes a plurality of mesas, each mesa including an epitaxial Group III nitride-based multi-layer structure, an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix, and a metallization structure including a gate finger and a drain finger arranged on the top surface of each mesa, a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of mesas, each mesa comprising an epitaxial Group III nitride-based multi-layer structure;   an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix; and   a metallization structure comprising:
 a gate finger and a drain finger arranged on the top surface of each mesa; 
 a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and 
 a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the drain bus and the gate bus are at least partially arranged on the upper surface of the insulating matrix, and wherein the metallization structure further comprises:
 a source region arranged on the insulating layer and extending between the first mesa and the second mesa.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the metallization structure further comprises:
 a source via extending through the insulating matrix, the source via being electrically coupled to the source region; and   a metallic layer on the lower surface of the insulating layer.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the metallic layer entirely covers a rear surface of the semiconductor device. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the metallic layer comprises a plurality of discrete regions arranged on the rear surface of the semiconductor device. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the insulating matrix comprises an oxide or a nitride. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the III-V semiconductor plurality of mesas are each connected to one another by a base substrate, and wherein the semiconductor device further comprises a parasitic channel suppression region at an interface between the insulating matrix and a first surface of the base substrate. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the parasitic channel suppression region comprises charge traps. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the parasitic channel suppression region comprises implanted species ions selected from the group consisting of Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si and Al. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the parasitic channel suppression region comprises a highly resistive region. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the metallization structure electrically couples the mesas together so that two or more mesas form a single switch or transistor device.