Bonded device structures with improved stress distribution and reduced cracking and methods of making the same

Abstract

A bonded device structure includes a carrier structure, an integrated circuit (IC) die bonded to a surface of the carrier structure via a bonding layer, where the IC die includes an eave vertically separated from and overlying the surface of the carrier structure, a bay region is located between the eave and the surface of the carrier structure, and a molding portion is located within the bay region. Various characteristics of the bay region and/or the molding compound may be engineered to provide improved stress distribution and reduce cracking defects. In some embodiments, a ratio of the width to height of the bay region may be >1. In some embodiments, a void ratio of the molding compound may be between 0.2 and 0.4.

What is claimed is: 
     
         1 . A bonded device structure, comprising:
 a carrier structure;   an integrated circuit (IC) die bonded to a surface of the carrier structure via a bonding layer, the IC die comprising an eave over the surface of the carrier structure, wherein a bay region is located between the eave and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay region is at least one; and   a molding portion laterally surrounding the IC die and located within the bay region between the surface of the carrier structure and the eave.   
     
     
         2 . The bonded device structure of  claim 1 , wherein the bay region is located between a lower surface of the eave, the surface of the carrier structure, and a sidewall extending between the lower surface of the eave and the surface of the carrier structure. 
     
     
         3 . The bonded device structure of  claim 2 , wherein the width dimension of the bay region is equal to an average of horizontal width dimensions of the bay region along a top surface of the bay region and a bottom surface of the bay region, and the height dimension of the bay region is equal to an average of vertical height dimensions of the bay region on inner and outer sides of the bay region, and wherein the ratio of the width dimension to the height dimension of the bay region is equal to or less than 80. 
     
     
         4 . The bonded device structure of  claim 3 , wherein a first angle between the sidewall and the lower surface of the eave is between 10° and 170° and a second angle between the sidewall and the surface of the carrier structure is between 10° and 170°. 
     
     
         5 . The bonded device structure of  claim 3 , wherein the horizontal width dimension of the bay region along the top surface of the bay region is equal to or less than 100 μm, the horizontal width dimension of the bay region along the bottom surface of the bay region is between 0.5 and 1.5 times the horizontal width dimension of the bay region along the top surface of the bay region, and the vertical height dimension of the bay region on the inner side of the bay region is equal to or greater than 1 μm. 
     
     
         6 . The bonded device structure of  claim 3 , wherein the IC die comprises a thickness dimension along a side surface of the IC die, a horizontal width dimension of the eave is greater than 1/100th of the thickness dimension of the IC die, and the vertical height dimension of the bay region on the inner side of the bay region is greater than 1/200th of the thickness dimension of the IC die and less than ½ of the thickness dimension of the IC die. 
     
     
         7 . The bonded device structure of  claim 1 , wherein the bay region has a rectangular, truncated parallelogram, or irregular polygon shape in a vertical cross-section. 
     
     
         8 . The bonded device structure of  claim 2 , further comprising at least one protective film over a side surface of the IC die and within the bay region over the lower surface of the eave and the sidewall, and the at least one protective film is located between IC die and the molding portion. 
     
     
         9 . The bonded device structure of  claim 1 , wherein a ratio of a total volume of voids in the molding portion to a total volume of molding compound in the molding portion is between 0.2 and 0.4. 
     
     
         10 . The bonded device structure of  claim 1 , wherein the IC die comprises a logic die, a memory die, an analog die, an RF die, an integrated passive device (IPD) die, or a dummy die, and the carrier structure comprises a substrate, an interposer, a semiconductor die, or a semiconductor wafer. 
     
     
         11 . The bonded device structure of  claim 1 , wherein the bonding layer of the IC die comprises a plurality of bonding pads embedded in a dielectric material and the bonding layer of the IC die is bonded to a corresponding bonding layer of the carrier structure via a metal-to-metal and dielectric-to-dielectric direct bond. 
     
     
         12 . The bonded device structure of  claim 1 , wherein the IC die comprises a first IC die, and the bonded device structure further comprises a second IC die bonded over the first IC die, the second IC die comprising an eave and a bay region underlying the eave, and a ratio of a width dimension to a height dimension of the bay region underlying the eave of the second IC die is at least one, and the molding portion laterally surrounds the second IC die and is located within the bay region underlying the eave of the second IC die. 
     
     
         13 . A bonded device structure, comprising:
 a carrier structure;   at least one integrated circuit (IC) die bonded to a surface of the carrier structure via a bonding layer, each IC die comprising an eave over the surface of the carrier structure, wherein a bay region is located between the eave and the surface of the carrier structure; and   a molding portion laterally surrounding each IC die and located within the bay region between the surface of the carrier structure and the eave of each IC die, and a ratio of a total volume of voids in the molding portion to a total volume of molding compound in the molding portion is between 0.2 and 0.4.   
     
     
         14 . The bonded device structure of  claim 13 , wherein the bonded device structure comprises a multi-tier bonded device structure comprising a plurality of IC dies, wherein one or more first IC dies bonded to the surface of the carrier structure form a first tier of IC dies and one or more second IC dies bonded over the first IC dies form a second tier of IC dies, each of the first IC dies and the second IC dies comprising an eave with a bay region underlying the eave, and the molding portion laterally surrounds each of the first IC dies and the second IC dies and is located within each of the bay regions underlying the eaves of the first IC dies and the second IC dies. 
     
     
         15 . The bonded device structure of  claim 14 , wherein a protective film is provided over surfaces of each IC die having a keep-out-zone of 20 μm or less. 
     
     
         16 . The bonded device structure of  claim 14 , wherein the bay regions underlying the eaves of the one or more first IC dies and the one or more second IC dies have non-uniform shapes. 
     
     
         17 . A method of fabricating a bonded device structure, comprising:
 forming a bonding layer over a semiconductor substrate;   performing a plasma dicing process to remove portions of the bonding layer and form an opening having a recessed surface that is recessed relative to an upper surface of the bonding layer and a sidewall extending between the recessed surface and an upper surface of the bonding layer;   performing a dicing process through the semiconductor substrate to provide an integrated circuit (IC) die;   bonding the bonding layer to a surface of a carrier structure to form a bonded device structure, wherein the upper surface of the bonding layer contacts the surface of the carrier structure, the IC die comprises an eave over the surface of the carrier structure, and a bay region is located between the eave and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay region is at least one; and   forming a molding portion laterally surrounding the IC die and within the bay region.   
     
     
         18 . The method of  claim 17 , wherein forming the molding portion comprises controlling a curing temperature and a heating rate of a molding process such that a ratio of a total volume of voids in the molding portion to a total volume of molding compound in the molding portion is between 0.2 and 0.4. 
     
     
         19 . The method of  claim 17 , further comprising:
 performing a laser grooving process to form a groove around the periphery of the IC die prior to performing the dicing process through the semiconductor substrate, wherein following the laser grooving process, at least a portion of the recessed surface remains between the groove and the sidewall.   
     
     
         20 . The method of  claim 17 , wherein the bonding layer comprises a first bonding layer comprising a plurality of bonding pads laterally surrounded by a dielectric material, and wherein bonding the first bonding layer to the surface of the carrier structure comprises:
 bringing the IC die into contact with the carrier structure such that the upper surface of the bonding layer contacts a second bonding layer on the carrier structure, where each of the plurality of bonding pads of the first bonding layer contacts a corresponding bonding pad of the second bonding layer; and   performing an annealing process to promote interdiffusion between the bonding pads of the first bonding layer and the corresponding bonding pads of the second bonding layer.