Stacked integrated circuit devices including logic die and memory stacks

Abstract

A stacked IC device includes a first memory stack including two or more memory dies coupled to a substrate and a second memory stack including two or more memory dies coupled to the substrate. The stacked IC device also includes a logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack and electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack. The stacked IC device further includes a patch component disposed in a region between the first memory stack and the second memory stack. The patch component includes conductors that electrically connect the logic die to the substrate.

1 . A device comprising:
 a first memory stack comprising two or more memory dies coupled to a substrate;   a second memory stack comprising two or more memory dies coupled to the substrate;   a logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack and electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack; and   a patch component disposed in a region between the first memory stack and the second memory stack, the patch component including conductors that electrically connect the logic die to the substrate.   
     
     
         2 . The device of  claim 1 , wherein the first memory stack comprises a high bandwidth memory (HBM) stack. 
     
     
         3 . The device of  claim 1 , wherein the top die of the first memory stack comprises a memory controller for the two or more memory dies of the first memory stack. 
     
     
         4 . The device of  claim 1 , wherein a body of the patch component comprises mold compound, and wherein the conductors comprise through mold vias extending through the mold compound. 
     
     
         5 . The device of  claim 1 , wherein a body of the patch component comprises a multilayer structure, and wherein the conductors comprise stacked and electrically connected conductors extending through layers of the multilayer structure. 
     
     
         6 . The device of  claim 1 , wherein a body of the patch component comprises a core layer, and wherein the conductors comprise vias extending through the core layer. 
     
     
         7 . The device of  claim 1 , wherein a body of the patch component comprises a semiconductor layer, and wherein one or more of the conductors comprises a through silicon via extending through the semiconductor layer. 
     
     
         8 . The device of  claim 1 , wherein the patch component includes active circuit components, passive circuit components, or both. 
     
     
         9 . The device of  claim 1 , further comprising:
 one or more additional memory stacks comprising two or more memory dies coupled to the substrate; and   a second logic die electrically connected to memory dies of the one or more additional memory stacks through face-to-face connections to a top die of each of the one or more additional memory stacks,   wherein the conductors of the patch component electrically connect the second logic die to the substrate.   
     
     
         10 . The device of  claim 9 , further comprising redistribution layers between the logic die and the first memory stack, between the logic die and the second memory stack, between the second logic die and the one or more additional memory stacks, and electrically connecting the logic die to the second logic die. 
     
     
         11 . The device of  claim 9 , wherein the logic die is electrically connected to the second logic die through the patch component. 
     
     
         12 . A device comprising:
 a first memory stack comprising two or more memory dies coupled to a substrate;   a second memory stack comprising two or more memory dies coupled to the substrate;   a first logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack;   a second logic die electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack; and   a patch component disposed in a region between the first memory stack and the second memory stack, the patch component including first conductors that electrically connect the first logic die to the substrate and second conductors that electrically connect the second logic die to the substrate.   
     
     
         13 . The device of  claim 12 , wherein the first memory stack comprises a first high bandwidth memory stack and the second memory stack comprises a second high bandwidth memory stack. 
     
     
         14 . The device of  claim 12 , wherein the top die of the first memory stack comprises a first memory controller for the two or more memory dies of the first memory stack, and the top die of the second memory stack comprises a second memory controller for the two or more memory dies of the second memory stack. 
     
     
         15 . The device of  claim 12 , wherein the first logic die and the second logic die are electrically connected to one another through the patch component. 
     
     
         16 . The device of  claim 12 , further comprising redistribution layers disposed between the first logic die and the first memory stack, between the second logic die and the second memory stack, and electrically connecting the first logic die to the second logic die. 
     
     
         17 . A method comprising:
 coupling a plurality of memory stacks to a substrate, each memory stack comprising two or more memory dies;   electrically connecting a patch component to the substrate in a region between two or more memory stacks of the plurality of memory stacks; and   electrically connecting a logic die to the substrate through the patch component, and, face-to-face, to top dies of the two or more memory stacks.   
     
     
         18 . The method of  claim 17 , further comprising electrically connecting a second logic die to the substrate through the patch component, and, face-to-face, to top dies of two or more additional memory stacks of the plurality of memory stacks. 
     
     
         19 . The method of  claim 18 , further comprising electrically connecting the logic die to the second logic die through the patch component. 
     
     
         20 . The method of  claim 18 , further comprising electrically connecting the logic die to the second logic die through redistribution layers.