Power semiconductor device including gate with improved reliability

Abstract

A power semiconductor device including a first gate electrode layer recessed into a semiconductor substrate, the first gate electrode layer being configured to extend in a first direction for a first length and a second gate electrode layer configured to extend in the first direction on a surface of the semiconductor substrate, the second gate electrode layer having a second length shorter than the first length, and configured to contact a first side surface of the first gate electrode layer.

What is claimed is: 
     
         1 . A power semiconductor device, comprising:
 a first gate electrode layer recessed into a semiconductor substrate, the first gate electrode layer being configured to extend in a first direction for a first length; and   a second gate electrode layer configured to extend in the first direction on a surface of the semiconductor substrate, the second gate electrode layer having a second length shorter than the first length, and configured to contact a first side surface of the first gate electrode layer.   
     
     
         2 . The power semiconductor device of  claim 1 , further comprising:
 an intermediate insulating layer configured to contact the first side surface of the first gate electrode layer and to contact a second side surface of the second gate electrode layer.   
     
     
         3 . The power semiconductor device of  claim 2 , further comprising:
 a bottom insulating layer disposed under the first gate electrode layer, the second gate electrode layer, and the intermediate insulating layer.   
     
     
         4 . The power semiconductor device of  claim 2 , further comprising:
 a top insulating layer disposed on the first gate electrode layer, the second gate electrode layer, and the intermediate insulating layer.   
     
     
         5 . The power semiconductor device of  claim 4 , wherein the top insulating layer is configured to contact one or more of another first side surface of the first gate electrode layer and another second side surface of the second gate electrode layer. 
     
     
         6 . The power semiconductor device of  claim 4 , further comprising:
 a source electrode layer disposed on the top insulating layer and configured to contact a third side surface of the top insulating layer.   
     
     
         7 . The power semiconductor device of  claim 3 , further comprising:
 a source region disposed on the surface of the semiconductor substrate inside the semiconductor substrate, the source region being configured to contact the bottom insulating layer, and comprising a first conductive type impurity; and   a body region configured to contact a lower surface of the source region, and to contact a lower surface of the bottom insulating layer, and comprising a second conductive type impurity.   
     
     
         8 . The power semiconductor device of  claim 7 , further comprising:
 a drift region disposed under the body region inside the semiconductor substrate and comprising the first conductive type impurity; and   a drain electrode layer disposed under the drift region.   
     
     
         9 . The power semiconductor device of  claim 2 , wherein the first gate electrode layer comprises one or more of poly-silicon, doped poly-silicon, a metal, a metal nitride, and a metal silicide,
 wherein the second gate electrode layer comprises a second material identical to a first material of the first gate electrode layer, and   wherein the intermediate insulating layer comprises one or more of silicon oxide, silicon nitride, germanium oxide, germanium nitride, hafnium oxide, zirconium oxide, and aluminum oxide.   
     
     
         10 . The power semiconductor device of  claim 1 , wherein the semiconductor substrate comprises a third material having a third band gap greater than a first band gap of silicon. 
     
     
         11 . A power semiconductor device, comprising:
 a planar gate electrode layer comprising:
 first gate regions extending in a first direction on a surface of a semiconductor substrate, the first gate regions being respectively configured to be spaced apart from each other in a second direction; and 
 second gate regions disposed between the first gate regions on the surface of the semiconductor substrate, the second gate regions being respectively configured to be spaced apart from each other in the first direction; and 
   a trench gate electrode layer comprising third gate regions extending from the first gate regions, respectively, into an interior of the semiconductor substrate.   
     
     
         12 . The power semiconductor device of  claim 11 , further comprising:
 an intermediate insulating layer configured to be surrounded by the first gate regions and the second gate regions on the surface of the semiconductor substrate.   
     
     
         13 . The power semiconductor device of  claim 12 , further comprising:
 a bottom insulating layer disposed under each of the second gate regions and each of the third gate regions.   
     
     
         14 . The power semiconductor device of  claim 12 , further comprising:
 a top insulating layer disposed on each of the first gate regions, each of the second gate regions, and the intermediate insulating layer.   
     
     
         15 . The power semiconductor device of  claim 14 , wherein the top insulating layer is configured to contact a first side surface of the first gate region and a second side surface of the second gate region. 
     
     
         16 . The power semiconductor device of  claim 14 , further comprising:
 a source electrode layer disposed on the top insulating layer and being configured to contact a third side surface of the top insulating layer.   
     
     
         17 . The power semiconductor device of  claim 13 , further comprising:
 a source region disposed on the surface of the semiconductor substrate inside the semiconductor substrate, the source region being configured to contact the bottom insulating layer, and comprising a first conductive type impurity; and   a body region configured to contact a lower surface of the source region, to contact a lower surface of the bottom insulating layer, and comprising a second conductive type impurity.   
     
     
         18 . The power semiconductor device of  claim 17 , further comprising:
 a drift region disposed under the body region inside the semiconductor substrate and comprising the first conductive type impurity; and   a drain electrode layer disposed under the drift region.   
     
     
         19 . The power semiconductor device of  claim 12 , wherein the planar gate electrode layer comprises one or more of poly-silicon, doped poly-silicon, a metal, a metal nitride, and a metal silicide,
 wherein the trench gate electrode layer comprises a first material identical to a second material of the planar gate electrode layer, and   wherein the intermediate insulating layer comprises one or more of silicon oxide, silicon nitride, germanium oxide, germanium nitride, hafnium oxide, zirconium oxide, and aluminum oxide.   
     
     
         20 . The power semiconductor device of  claim 11 , wherein the semiconductor substrate comprises a third material having a third band gap greater than a first band gap of silicon.