US2025279283A1PendingUtilityA1

Selective etching of alternating layers of silicon oxide and silicon nitride for high aspect ratio contacts

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Assignee: APPLIED MATERIALS INCPriority: Mar 1, 2024Filed: Mar 1, 2024Published: Sep 4, 2025
Est. expiryMar 1, 2044(~17.6 yrs left)· nominal 20-yr term from priority
Inventors:Sonam D. SherpaAlok Ranjan
H10P 14/6532H10P 50/283H01J 37/32146H01J 37/32449H01J 2237/3346H01L 21/0234H01L 21/31116
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Claims

Abstract

Exemplary semiconductor processing methods may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include alternating layers of silicon nitride and silicon oxide. The methods may include forming plasma effluents of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor. The contacting may selectively etch an exposed portion of silicon nitride. The methods may include introducing a phosphorous-and-fluorine-containing precursor into the processing region of the semiconductor processing chamber while maintaining a flow of the fluorine-containing precursor. The methods may include forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor. The contacting may selectively etch an exposed portion of silicon oxide.

Claims

exact text as granted — not AI-modified
1 . A semiconductor processing method comprising:
 flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region, and wherein the substrate comprises alternating layers of silicon nitride and silicon oxide;   forming plasma effluents of the fluorine-containing precursor;   contacting the substrate with the plasma effluents of the fluorine-containing precursor, wherein the contacting selectively etches an exposed portion of silicon nitride;   introducing a phosphorous-and-fluorine-containing precursor into the processing region of the semiconductor processing chamber while maintaining a flow of the fluorine-containing precursor;   forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor; and   contacting the substrate with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting selectively etches an exposed portion of silicon oxide.   
     
     
         2 . The semiconductor processing method of  claim 1 , wherein the fluorine-containing precursor comprises hydrogen fluoride (HF). 
     
     
         3 . The semiconductor processing method of  claim 1 , wherein the phosphorous-and-fluorine-containing precursor comprises phosphorous trifluoride (PF 3 ). 
     
     
         4 . The semiconductor processing method of  claim 1 , wherein a flow rate of the fluorine-containing precursor is greater than or about 100 sccm. 
     
     
         5 . The semiconductor processing method of  claim 1 , wherein a flow rate of the phosphorous-and-fluorine-containing precursor is less than or about 50 sccm. 
     
     
         6 . The semiconductor processing method of  claim 1 , wherein the fluorine-containing precursor is carbon-free. 
     
     
         7 . The semiconductor processing method of  claim 1 , wherein a source plasma power is pulsed while forming the plasma effluents of the fluorine-containing precursor and the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor. 
     
     
         8 . The semiconductor processing method of  claim 1 , further comprising:
 applying a bias power while contacting the stacked layers with the plasma effluents of the fluorine-containing precursor and the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor.   
     
     
         9 . The semiconductor processing method of  claim 8 , wherein the bias power is greater than or about 100 W. 
     
     
         10 . The semiconductor processing method of  claim 8 , wherein the bias power is pulsed while contacting the stacked layers with the plasma effluents of the fluorine-containing precursor and the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor. 
     
     
         11 . The semiconductor processing method of  claim 1 , wherein the method is performed at a chamber operating pressure of less than or about 500 mTorr. 
     
     
         12 . The semiconductor processing method of  claim 1 , wherein the method is performed at a substrate operating temperature of less than or about 0° C. 
     
     
         13 . A semiconductor processing method comprising:
 i) flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region, wherein the substrate comprises alternating layers of silicon nitride and silicon oxide, and wherein the substrate comprises a patterned resist material overlying the alternating layers of silicon nitride and silicon oxide;   ii) forming plasma effluents of the fluorine-containing precursor;   iii) contacting the stacked layers with the plasma effluents of the fluorine-containing precursor, wherein the contacting selectively etches an exposed layer of silicon nitride;   iv) flowing a phosphorous-and-fluorine-containing precursor into the processing region of the semiconductor processing chamber with the fluorine-containing precursor;   v) forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor;   vi) contacting the stacked layers with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting selectively etches an exposed layer of silicon oxide; and   vii) repeating operations i) through vi) for at least a second cycle.   
     
     
         14 . The semiconductor processing method of  claim 13 , wherein the fluorine-containing precursor further comprises hydrogen. 
     
     
         15 . The semiconductor processing method of  claim 13 , wherein an etch rate of the exposed layer of silicon nitride is greater than or about 250 nm/min. 
     
     
         16 . The semiconductor processing method of  claim 13 , wherein an etch rate of the exposed layer of silicon nitride is greater than or about 400 nm/min. 
     
     
         17 . The semiconductor processing method of  claim 13 , operations i) through vi) are repeated for at least ten cycles. 
     
     
         18 . The semiconductor processing method of  claim 13 , wherein the method is performed at a substrate operating temperature of less than or about −20° C. 
     
     
         19 . A semiconductor processing method comprising:
 flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region, and wherein the substrate comprises alternating layers of silicon nitride and silicon oxide;   forming plasma effluents of the fluorine-containing precursor;   contacting the substrate with the plasma effluents of the fluorine-containing precursor, wherein the contacting etches an exposed portion of silicon nitride relative to silicon oxide at a selectivity greater than or about 5:1;   introducing a phosphorous-and-fluorine-containing precursor into the processing region of the semiconductor processing chamber while maintaining a flow of the fluorine-containing precursor;   forming plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, and   contacting the substrate with the plasma effluents of the fluorine-containing precursor and the phosphorous-and-fluorine-containing precursor, wherein the contacting etches an exposed portion of silicon oxide relative to silicon nitride at a selectivity greater than or about 5:1.   
     
     
         20 . The semiconductor processing method of  claim 19 , wherein a flow rate ratio of the fluorine-containing precursor to the phosphorous-and-fluorine-containing precursor is greater than or about 30:1.

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