Cfet type transistor device

Abstract

A CFET transistor device, including: a substrate; a first semiconductor nanosheet and a second semiconductor nanosheet; an insulating layer arranged between the first and second nanosheets; a first gate arranged around a first part of the first nanosheet, and a second gate arranged around a first part of the second nanosheet; first inner spacers arranged against second parts of the first nanosheet, between which the first part of the first nanosheet is arranged, and second inner spacers arranged against second parts of the second nanosheet between which the first part is arranged; and wherein the first and second inner spacers respectively include first and second low-permittivity dielectric materials different from each other.

1 . Device with complementary field-effect transistors, comprising:
 a substrate;   at least one first semiconductor nanosheet and at least one second semiconductor nanosheet, the first semiconductor nanosheet being arranged between the second semiconductor nanosheet and the substrate;   an insulating layer arranged between the first and second semiconductor nanosheets;   a first gate arranged around a first part of the first semiconductor nanosheet, and a second gate arranged around a first part of the second semiconductor nanosheet;   first inner spacers arranged against second parts of the first semiconductor nanosheet, between which the first part of the first semiconductor nanosheet is arranged, and   second inner spacers arranged against second parts of the second semiconductor nanosheet, between which the first part of the second semiconductor nanosheet is arranged;   wherein the first and second inner spacers respectively comprise first and second low-permittivity dielectric materials, the first and second dielectric materials being different from each other;   and wherein the insulating layer is arranged opposite all the surfaces of the first and second semiconductor nanosheets located opposite the insulating layer.   
     
     
         2 . Device according to  claim 1 , wherein the first and second semiconductor nanosheets respectively comprise first and second semiconductor materials having crystalline orientations different from each other. 
     
     
         3 . Device according to  claim 1 , wherein the first and second gates respectively comprise first and second metallic materials different from each other. 
     
     
         4 . Device according to  claim 1 , wherein at least part of the first gate is in contact with at least part of the second gate, or wherein the first and second gates are dissociated and insulated from each other. 
     
     
         5 . Device according to  claim 4 , wherein, when the first and second gates are dissociated and insulated from each other, each of the first and second gates is comb-shaped. 
     
     
         6 . Method of manufacturing a device with complementary field-effect transistors, comprising at least:
 the forming of a structure comprising at least one substrate, first and second semiconductor nanosheets, the first semiconductor nanosheet being arranged between the second semiconductor nanosheet and the substrate, and an insulating layer arranged between the first and second semiconductor nanosheets;   the forming of first inner spacers arranged against second parts of the first semiconductor nanosheet, and of second inner spacers arranged against second parts of the second semiconductor nanosheet, the first and second inner spacers respectively comprising first and second low-permittivity dielectric materials, the first and second dielectric materials being different from each other, and such that the first inner spacers are formed before or after the second inner spacers;   the forming of a first gate around a first part of the first semiconductor nanosheet arranged between the second parts of the first semiconductor nanosheet, and of a second gate around a first part of the second semiconductor nanosheet arranged between the second parts of the second semiconductor nanosheet;   wherein, at the end of these steps, the insulating layer is arranged opposite all the surfaces of the first and second semiconductor nanosheets facing the insulating layer;   and wherein the forming of the structure comprises at least:   the forming of a first stack of layers comprising at least one first semiconductor layer arranged between two first sacrificial layers of a material capable of being selectively etched over the first semiconductor layer, and comprising a first dielectric layer;   the forming of a second stack of layers comprising at least one second semiconductor layer arranged between two second sacrificial layers of a material capable of being selectively etched over the second semiconductor layer, and comprising a second dielectric layer;   the bonding of the first and second dielectric layers to each other and forming the insulating layer together.   
     
     
         7 . Method according to  claim 6 , wherein the forming of the structure further comprises, after the bonding of the first and second dielectric layers to each other, an etching of at least one trench implemented through the first and second stacks of layers and the insulating layer. 
     
     
         8 . Method according to  claim 7 , wherein the forming of the second inner spacers comprises at least:
 the forming of a sacrificial gate in the trench and on remaining portions of the structure obtained at the end of the etching of the trench, then the forming of gate spacers around the sacrificial gate, then   the etching of parts of the remaining portions of the structure not covered by the sacrificial gate and the gate spacers, through the layers of the second stack and a first part of the insulating layer without crossing a bonding interface between the first and second dielectric layers, then   the etching of parts of remaining portions of the second sacrificial layers arranged against the second parts of the second semiconductor nanosheet, then   the forming of a layer of the second low-permittivity dielectric material such that portions of this layer arranged against second parts of the second semiconductor nanosheet form the second inner spacers.   
     
     
         9 . Method according to  claim 8 , wherein the forming of the first inner spacers comprises at least, after the forming of the layer of the second low permittivity dielectric material:
 the etching of parts of the remaining portions of the structure not covered by the sacrificial gate, the gate spacers, and by parts of the layer of the second low-permittivity dielectric material which rest on a second part of the insulating layer comprising the bonding interface and which cover the ends of the second parts of the second semiconductor nanosheet, through the layers of the first stack and the second part of the insulating layer, then   the etching of parts of remaining portions of the first sacrificial layers arranged against the second parts of the first semiconductor nanosheet, then the forming of a layer of the first low-permittivity dielectric material in such a way that portions of this layer arranged against second parts of the first semiconductor nanosheet form the first inner spacers.   
     
     
         10 . Method according to  claim 9 , further comprising, between the forming of the first and second inner spacers and the forming of the first and second gates:
 the forming of first source or drain regions against ends of second the parts of the first semiconductor nanosheet, then   the removal of the parts of the layer of the second low-permittivity dielectric material covering the ends of the second parts of the second semiconductor nanosheet, then   the forming of second source or drain regions against ends of second parts of the second semiconductor nanosheet.   
     
     
         11 . Method according to  claim 10 , wherein the forming of the first and second source or drain regions each comprise the implementation of an epitaxy, and further comprising, between the forming of the first and second source or drain regions, a deposition of insulating material covering at least the first source and drain regions. 
     
     
         12 . Method according to  claim 9 , further comprising, between the forming of the first and second inner spacers and the forming of the first and second gates or during the forming of the first and second gates, an etching of the remaining portions of the first and second sacrificial layers. 
     
     
         13 . Method according to  claim 8 , wherein the forming of the first and second gates comprises an etching of the sacrificial gate, followed by successive depositions of at least one first metallic material forming the first gate and of at least one second metallic material different from the first metallic material and forming the second gate, and such that at least part of the first gate is in contact with at least part of the second gate. 
     
     
         14 . Method according to  claim 6 , wherein the forming of the first and second gates comprises:
 an etching of a first part of the sacrificial gate so as to form an access to the first part of the second semiconductor nanosheet, then   a deposition of materials forming the second gate, then   an etching of a second part of the sacrificial gate so as to form an access to the first part of the first semiconductor nanosheet, then   a deposition of materials forming the first gate such that the first and second gates are dissociated and insulated from each other.