Package and manufacturing method thereof

Abstract

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

What is claimed is: 
     
         1 . A package, comprising:
 a first die having a first bonding structure, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;   a second die having a semiconductor substrate and a second bonding structure over the semiconductor substrate, wherein the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate, the first connectors are in physical contact with the second connectors, and the first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer;   an encapsulant laterally encapsulating the second die; and   through insulating vias (TIV) aside the second die.   
     
     
         2 . The package according to  claim 1 , wherein the encapsulant covers a portion of a top surface of the first dielectric layer and the sidewalls of the second dielectric layer. 
     
     
         3 . The package according to  claim 1 , wherein each first connector of the first connectors has a via portion and a trench portion stacked on the via portion, each second connector of the second connectors has a via portion and a trench portion stacked on the via portion, and the trench portion of the second connector is in physical contact with the trench portion of the first connector. 
     
     
         4 . The package according to  claim 1 , wherein the first bonding structure further comprises auxiliary connectors embedded in the first dielectric layer, and the TIVs are in physical contact with the auxiliary connectors. 
     
     
         5 . The package structure according to  claim 1 , wherein the second die further comprises through semiconductor vias (TSV) penetrating through the semiconductor substrate of the second die. 
     
     
         6 . The package structure according to  claim 5 , further comprising:
 under-ball metallurgy (UBM) patterns disposed on the encapsulant, wherein the UBM patterns are connected to the TIVs and the TSVs; and   conductive terminals disposed on the UBM patterns.   
     
     
         7 . The package structure according to  claim 6 , wherein at least one of the TSVs and at least one of the TIVs are connected to a same UBM pattern. 
     
     
         8 . The package structure according to  claim 6 , wherein multiple TSVs are connected to a same UBM pattern. 
     
     
         9 . A package, comprising:
 a first die, comprising:
 a first semiconductor substrate; 
 first connectors over the first semiconductor substrate; and 
 a first dielectric layer laterally encapsulating the first connectors; 
   a second die bonded to the first die, comprising:
 a second semiconductor substrate; 
 second connectors over the second semiconductor substrate, wherein the second connectors are in physical contact with the first connectors, and the first connectors and the second connectors are arranged on two opposite sides of an interface between the first die and the second die; and 
 a second dielectric layer laterally encapsulating the second connectors, wherein sidewalls of the second dielectric layer are aligned with sidewalls of the second semiconductor substrate; and 
   an encapsulant laterally encapsulating the second die, wherein the encapsulant covers a portion of a top surface of the first dielectric layer and the sidewalls of the second dielectric layer.   
     
     
         10 . The package according to  claim 9 , wherein the first die further comprises:
 a first interconnection structure sandwiched between the first dielectric layer and the first semiconductor substrate; and   auxiliary connectors embedded in the first dielectric layer, wherein the auxiliary connectors are electrically connected to the first interconnection structure.   
     
     
         11 . The package according to  claim 10 , further comprising through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs are in physical contact with the auxiliary connectors. 
     
     
         12 . The package according to  claim 11 , wherein multiple auxiliary connectors are in physical contact with a same TIV. 
     
     
         13 . The package according to  claim 11 , wherein the second die further comprises:
 a second interconnection structure sandwiched between the second dielectric layer and the second semiconductor substrate; and   through semiconductor vias (TSV) penetrating through the second semiconductor substrate, wherein the TSVs have protruding portions protruding out from the second semiconductor substrate.   
     
     
         14 . The package structure according to  claim 13 , wherein the protruding portions of the TSVs are wrapped around by the encapsulant. 
     
     
         15 . The package structure according to  claim 13 , further comprising:
 under-ball metallurgy (UBM) patterns disposed on the encapsulant, wherein the UBM patterns are connected to the TIVs and the TSVs; and   conductive terminals disposed on the UBM patterns.   
     
     
         16 . The package structure according to  claim 15 , wherein multiple TSVs are connected to a same UBM pattern. 
     
     
         17 . A manufacturing method of a package, comprising:
 providing a semiconductor wafer comprising a first bonding structure, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;   providing a semiconductor die comprising a semiconductor substrate, a second bonding structure formed on the semiconductor substrate, and through semiconductor vias (TSV) embedded in the semiconductor substrate, the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, and sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate;   bonding the semiconductor die to the semiconductor wafer, such that the first connectors are in physical contact with the second connectors, and the first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer;   forming through insulating vias (TIV) aside the semiconductor die;   laterally encapsulating the semiconductor die and the TIVs by a first encapsulant; and   forming under-ball metallurgy (UBM) patterns and conductive terminals over the first encapsulant and the semiconductor die, wherein the UBM patterns are connected to the TIVs and the TSVs.   
     
     
         18 . The method according to  claim 17 , further comprising:
 after encapsulating the semiconductor die and the TIVs by the first encapsulant, removing a portion of the semiconductor die to form a recess; and   filling a second encapsulant into the recess such that a top surface of the second encapsulant is substantially coplanar with a top surface of the first encapsulant.   
     
     
         19 . The method according to  claim 18 , wherein the portion of the semiconductor die is removed such that at least a portion of each TSV is protruded from the semiconductor substrate of the semiconductor die. 
     
     
         20 . The method according to  claim 17 , wherein encapsulating the semiconductor die and the TIVs comprises:
 forming a first encapsulant material over the semiconductor wafer to encapsulate the semiconductor die and the TIVs; and   thinning the first encapsulant material and the semiconductor die until the TIVs and the TSVs are exposed.