Semiconductor dynamic memory device

Abstract

A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

What we claim is: 
     
       1. A semiconductor dynamic memory device comprising: 2 n , n being an integer of not less than 2, memory means each including a plurality of memory cells substantially arranged in a matrix form, and a plurality of word lines and data lines connected to said memory cells;   decoding means for selecting rows and columns of said 2 n  memory in accordance with N-bit, N being an integer larger than n, row address data and M-bit column address data, said N-bit row address data including n-bit address data which is selectively determined to designate a corresponding one of said 2 n  memory means;   a plurality of sense amplifier circuits connected to said 2 n  memory, respectively, for sensing and amplifying data on said data lines; and   driving means for selectively activating a predetermined number of said sense amplifier circuits in accordance with the content of m, m being a positive integer smaller than n, bit data included in said n-bit address data and keeping the rest of said plurality of sense amplifier circuits in a non-active state.   
     
     
       2. A semiconductor dynamic memory device according to claim 1, wherein said decoding means includes 2 n  row decoding circuits respectively connected to said 2 n  memory means and each connected to receive row address data, 2.sup.(n-1) column decoding circuits each connected to two of said 2 n  memory means, and logic means connected to permit column address data to be selectively transferred to said 2.sup.(n-1) column decoding circuits. 
     
     
       3. A semiconductor dynamic memory device according to claim 2, wherein n is set at 2, and said logic means permits the column address data to be selectively transferred to said 2.sup.(n-1) column decoding circuits in accordance with the value of the most significant bit in said row address data. 
     
     
       4. A semiconductor dynamic memory device according to claim 3, wherein said driving means includes selection means for selecting two of said 2 n  sense amplifier circuits in accordance with the value of a predetermined bit in said row address data. 
     
     
       5. A semiconductor dynamic memory device according to claim 2, wherein said driving means includes selection means for selecting two of said 2 n  sense amplifier circuits in accordance with the value of a predetermined bit in said row address data. 
     
     
       6. A semiconductor dynamic memory device according to claim 2, wherein n is set at 3, and said logic means permits the column address data to be selectively transferred to said 2.sup.(n-1) column decoding circuits in accordance with the value of the most significant bit and the value of a predetermined bit in said row address data. 
     
     
       7. A semiconductor dynamic memory device according to claim 6, wherein said driving means includes selection means for selecting two of said 2 n  sense amplifier circuits in accordance with the value of said predetermined bit and the value of another predetermined bit in said row address data. 
     
     
       8. A semiconductor dynamic memory device according to claim 2, wherein said driving means includes selection means for selecting two of said 2 n  sense amplifier circuits in accordance with the value of said predetermined bit and the value of another predetermined bit in said row address data.