Lead end grid array semiconductor package

Abstract

The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, whereby the lead ends are distributed in a grid array. The invention includes a lead end grid array semiconductor package employing the grid array type lead frame, which is as small as or similar to that of semiconductor chip in area while the lead ends are arrayed on one plane, farther distant way from neighboring ones but in a higher number per area, in such a manner that they form a grid array.

What is claimed is: 
     
       1. A lead end grid semiconductor package, comprising: a semiconductor chip;   a plurality of leads, extending to lead ends forming input and output terminals;   electrically connecting means for connecting bond pads attached to the semiconductor chip with the leads; and   a plastic encapsulating part for protecting the semiconductor chip, the electrically connecting means and the leads from external environment, said leads being classified into at least two lead groups by length in each of which at least a different plane direction-converting lead part is formed by at least one bending part, said lead ends being exposed out of a bottom region of the plastic encapsulating part corresponding to a semiconductor chip mounting region, with a formation of a grid array.   
     
     
       2. A lead end grid semiconductor package as set forth in claim 1, wherein each of the leads of at least one lead group of the at least two end groups by length has at least one identical plane direction-converting lead part. 
     
     
       3. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the lead ends of the leads classified into the at least two lead groups by length form at least a partially alternating grid array which is comprised of at least three alternating lines and at least three alternating rows. 
     
     
       4. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the number of the bending parts formed in the leads is set to be different in one lead group from another lead group. 
     
     
       5. A lead end grid semiconductor package as set forth in claim 1 wherein the number of the bending parts varies among the leads of each lead group. 
     
     
       6. A lead end grid semiconductor package as set forth in claim 2, wherein the identical plane direction-converting lead part is formed in the leads of at least two lead groups and the number of the identical plane direction-converting lead parts vary from one lead group to another lead group. 
     
     
       7. A lead end grid semiconductor package as set forth in claim 6, wherein the number of the identical plane direction lead parts vary in each lead group. 
     
     
       8. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein at least two leads are interconnected with a neighboring lead through at least one lead connecting part. 
     
     
       9. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein, all the leads are bent to at least two directions including a Z axis, extending to the respective lead ends. 
     
     
       10. A lead end grid semiconductor package as set forth in claim 2, wherein the identical plane direction-converting lead part is directed to at least one axis selected from XY axis, X axis and Y axis. 
     
     
       11. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the leads each are bent in a downward direction by a first bending part and extended to the same direction as before the bending by a second bending part. 
     
     
       12. A lead end grid semiconductor package as set forth in claim 11, wherein the first bending parts in all of the leads are positioned at the same distance away from the sides of the semiconductor package and the second bending parts are formed near the first bending parts at the same distance away from a dambar supporting the leads. 
     
     
       13. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the leads ends each are formed into an expanded square form wider than the leads. 
     
     
       14. A lead end grid semiconductor package as set forth in claim 13, wherein each of the lead ends has a cylindrical lead end prominence at its bottom, forming input and output terminals. 
     
     
       15. A lead end grid semiconductor package as set forth in claim 14, wherein the lead end has at least one lead end tip formed beside at least one side of the lead end including the side to the direction of which the lead extends. 
     
     
       16. A lead end grid semiconductor package as set forth in claim 14, wherein the lead end prominences form a grid array which consists of at least three alternating lines and at least three alternating rows. 
     
     
       17. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the the leads form a lead frame and wherein the lead frame further comprises a semiconductor chip pad set. 
     
     
       18. A lead end grid semiconductor package as set forth in claim 17, wherein the semiconductor chip pad set consists of a plurality of rectangular pads, such pads being interconnected in a line by a supporting member. 
     
     
       19. A lead end grid semiconductor package as set forth in claim 18, wherein the rectangular pads are connected to a tie bar which is bent in the same patterns as those accomplished by the first and the second bending parts. 
     
     
       20. A lead end grid semiconductor package as set forth in claim 18, wherein the square pads and the rectangular pads have heat emission prominences at their bottoms. 
     
     
       21. A lead end grid semiconductor package as set forth in claim 17, wherein the semiconductor chip pad set comprises at least two semiconductor chip pads smaller in area than the semiconductor chip, at the opposite sides of the lead frame. 
     
     
       22. A lead end grid semiconductor package as set forth in claim 17, wherein the semiconductor chip pad set comprises at least one pad smaller in area than the semiconductor chip, said pad being positioned at the central region of the lead frame and supported by a tie bar. 
     
     
       23. A lead end grid semiconductor package as set forth in claim 1, wherein two leads, each extending from a side, are connected with each other to form one lead end at a corner of the package. 
     
     
       24. A lead end grid array semiconductor package as set forth in claim 1 or 2, wherein the exposed surface of each lead end is coated with platinum or palladium. 
     
     
       25. A lead end grid semiconductor package as set forth in claim 1, wherein the plastic encapsulating part encapsulates all of the four sides and the upper surface and the lower surface of the semiconductor chip. 
     
     
       26. A lead end grid semiconductor package as set forth in claim 25, wherein the electrically connecting means connects the bond pads formed on the semiconductor chip with the non-bent upper surfaces of the leads, from above. 
     
     
       27. A lead end grid semiconductor package as set forth in claim 25, wherein the electrically connecting means connects the bond pads formed beneath the semiconductor chip with non-bent upper surfaces of the leads, from above. 
     
     
       28. A lead end grid semiconductor package as set forth in claim 25, wherein the electrically connecting means are bumps or solder joints which connect the bond pads attached to the semiconductor chip with non-bent upper surfaces of the leads. 
     
     
       29. A lead end grid semiconductor package as set forth in one of claims 26 to 28, wherein the leads each are coated with silver or platinum at a part at which an electrical connection is accomplished. 
     
     
       30. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the bond pads are for signal input and output, are arranged beneath a central region of the semiconductor chip, and are electrically connected with a non-bent lower surface of the leads by bond wires, from below, and the plastic encapsulating part encapsulates only a lower portion of the semiconductor chip so that the area of the package is as small as that of the semiconductor chip. 
     
     
       31. A lead end grid semiconductor package as set forth in claim 30, wherein the exposed surfaces of the lead ends are coated with silver or palladium. 
     
     
       32. A lead end grid semiconductor package as set forth in claim 30, wherein the leads each are coated with silver or palladium at a part at which an electrical connection is accomplished. 
     
     
       33. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the plastic encapsulating part encapsulates a lower portion and four sides of the semiconductor chip so that the upper surface of the semiconductor chip is exposed to the exterior. 
     
     
       34. A lead end grid semiconductor package as set forth in claim 33, wherein the electrically connecting means are bond wires which connect the bond pads formed beneath the semiconductor chip with non-bent lower surfaces of the leads, from below. 
     
     
       35. A lead end grid semiconductor package as set forth in claim 33, wherein the electrically connecting means are bumps or solder joints which connect the bond pads formed beneath the semiconductor chip with non-bent upper surfaces of the leads. 
     
     
       36. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the bond pads are formed beneath the semiconductor chip and further including a heat sink attached to the semiconductor chip, said heat sink having an upper surface exposed to the exterior. 
     
     
       37. A lead end grid semiconductor package as set forth in claim 36, wherein the electrically connecting means are bond wires which connect the bond pads formed on the semiconductor chip with non-bent upper surfaces of the leads, from above. 
     
     
       38. A lead end grid semiconductor package as set forth in claim 36, wherein the electrically connecting means are bond wires which connect the bond pads formed beneath the semiconductor chip with non-bent lower surfaces of the leads, from below. 
     
     
       39. A lead end grid semiconductor package as set forth in claim 1 or 2, further comprising a second semiconductor chip, which is laminated on the upper surface of the existing semiconductor chip, the upper semiconductor chip having bond pads on its upper surface, which are electrically connected with the leads by bond wires and the lower semiconductor chip having bond pads beneath its lower surface, which are electrically connected with the leads by bumps or solder joints. 
     
     
       40. A lead end grid semiconductor package as set forth in claim 39, wherein the exposed surfaces of the lead ends are coated with platinum or palladium. 
     
     
       41. A lead end grid semiconductor package as set forth in claim 39, wherein the opposite ends of the leads to the lead ends are extended to the outside of the package and bent into the form of a seagull's wing or the form of a "J" character. 
     
     
       42. A lead end grid semiconductor package as set forth in claim 41, wherein the bent, opposite ends of the leads are fused with solder balls, at their inside. 
     
     
       43. A lead end grid semiconductor package as set forth in claim 1 or 2, wherein the opposite ends of the leads to the lead ends are extended to the outside of the package and bent into the form of a seagull's wing or the form of a "J" character. 
     
     
       44. A lead end grid semiconductor package as set forth in claim 43, wherein the bent, opposite ends of the leads are fused with solder balls, at their inside. 
     
     
       45. A lead end grid semiconductor package as set forth in claim 1, wherein the leads are classified into groups by length, with an extension direction in an X axis or a Y axis, each of the leads with an extension direction of an X axis being sequentially bent to a Z axis downward direction, an X axis direction and a Z axis direction by a first, a second and a third bending part, respectively, so that it extends in a step pattern, each of the leads with an extension direction of a Y axis being sequentially bent to a Z axis downward direction a Y axis direction and a Z axis downward by a first, a second and a third bending part, respectively, so that it extends in a step pattern. 
     
     
       46. A lead end grid semiconductor package as set forth in claim 2, wherein the leads are classified into groups by length and alternately arrayed with an extension direction in a X axis or a Y axis, the leads with an extension direction of an X axis being subject to either relatively long groups having identical plane Y axis direction-converting lead parts, in which the leads are sequentially bent in a Z axis downward direction and a Y axis direction by a first and a second bending part, respectively, or relatively short groups having no identical plane Y axis direction-converting lead parts, and in which the leads each are sequentially bent in a Z axis downward direction and an X direction by a first and second bending, respectively, and the leads with an extension direction in a Y axis each being sequentially bent in a Z axis downward direction and a Y axis direction by a first and a second bending part, respectively. 
     
     
       47. A lead end grid semiconductor package as set forth in claim 46, wherein the leads with an extension direction of an X axis, each having no identical plane Y axis direction-converting lead part, are slant bent in a XZ axis direction by the first bending part, and the other leads with an extension direction of an X axis, each having an identical plane Y axis direction-converting lead part and the leads with an extension direction of a Y axis are both slant bent in an YZ axis direction by the first bending parts. 
     
     
       48. A lead end grid semiconductor package as set forth in claim 1, wherein the leads are classified into groups by length and alternately arrayed with an extension direction of an X axis or a Y axis, the leads with an extension direction of an X axis being subject to either relatively long groups in which the leads each are sequentially bent to a Z axis downward direction, a Y axis direction and a Z axis downward direction by a first, a second and a third bending part, respectively, or relatively short groups in which the leads each are sequentially bent a Z axis downward direction an X axis direction and a Z axis downward direction by a first, a second and a third bending part, respectively, so that they extend in step patterns, and the leads with an extension direction of a Y axis each being sequentially bent to a Z axis downward direction, a Y axis direction and a Z axis downward direction by a first, a second and a third bending part, respectively, so that they extend in step patterns. 
     
     
       49. A lead end grid semiconductor package as set forth in one of claims 45 to 48, wherein the leads form a lead frame including a tie bar and further comprising a semiconductor chip pad smaller in area than the semiconductor chip which chip pad is supported by the tie bar at a central region of the lead frame, the lead ends forming a grid array on a plane lower than a plane of the semiconductor chip except for the region corresponding to the semiconductor chip pad. 
     
     
       50. A lead end grid semiconductor package as set forth in claim 46 or 47, wherein the lead ends are each formed into expanded planar forms which are wider than the leads and parallel to the semiconductor package. 
     
     
       51. A lead grid semiconductor package as set forth in claim 1, wherein the leads are classified into groups by length and alternatively arrayed with an extension direction of an X axis or a Y axis, the leads with an extension direction of an X axis being subject to either relatively long groups in which the leads each are sequentially bent to a Z axis downward direction, a Y axis direction, a Z axis upward direction, a Y axis direction and a Z axis downward direction by first to fifth bending parts, respectively, so that they extend in fallen "S" character patterns, or to relatively short groups or the longest group in which the leads each are sequentially bent to a Z axis downward direction, an X axis direction, a Z axis upward direction, an X axis direction and a Z axis downward direction by first to fifth bending parts, respectively, so that they extend in fallen "S" character patterns, and the leads with an extension direction of a Y axis each being sequentially bent to a Z axis downward direction, a Y axis direction, a Z axis upward direction, and a Y axis direction and a Z axis downward direction by first to fifth bending parts, respectively, so that they extend in a fallen "S" character pattern. 
     
     
       52. A lead end grid semiconductor package as set forth in claim 51, wherein the leads form a lead frame and wherein the leads subject to the longest group with an extension direction of an X axis and the leads subject to the longest group with an extension direction of a Y axis both extend below a central part of the lead frame. 
     
     
       53. A grid array type lead frame as set forth in claim 51 or 52, wherein the leads ends and the X axis or Y axis different plane direction-converting lead parts between the two different plane direction-converting lead parts formed by the bending to downward and upward Z axis are positioned on a plane lower than the plane of a semiconductor chip-mounting region. 
     
     
       54. A lead end grid semiconductor package as set forth in one of claims 45 to 48 or claim 51, wherein exposed surfaces of the lead ends are positioned on the same plane with the bottom of the plastic encapsulating part. 
     
     
       55. A lead end grid semiconductor package as set forth in one of claims 45 to 48 or claim 51, wherein the lead ends are protruded to the extent as large as the thickness of the leads, from the bottom of the plastic encapsulating part. 
     
     
       56. A lead end grid semiconductor package as set forth in claim 54, wherein the exposed surfaces of the lead ends are fused with solder balls.