Delay time control circuit

Abstract

A delay time control circuit controls delay times without a significant increase of power consumption or circuit components. The delay time control circuit for controlling delay times in a logic circuit includes a delay circuit having a plurality of serially connected gates, a pulse signal supplied to the delay circuit; a first group of gates which generates a reset pulse based on the pulse signal, a second group of gates which generates a set pulse based on the pulse signal, a flip-flop which is set by the set pulse and is reset by the reset pulse, an integrator which integrates an output signal of the flip-flop to produce an average voltage indicating a duty cycle of the output signal, a first delay time control voltage generator which compares the average voltage and a reference voltage indicating a delay time for the logic circuit and generates a first control voltage which is applied to the logic circuit, and a second delay time control voltage generator which receives the first control voltage and generates a second control voltage which is symmetrical to the first control voltage and is applied to the logic circuit.

What is claimed is: 
     
       1. A delay time control circuit for controlling delay times of a logic circuit which determines timings of test signals in a semiconductor test system, comprising: a delay circuit having a plurality of serially connected semiconductor gates which are the same type of semiconductor gates as in said logic circuit;   a pulse signal supplied to said delay circuit;   wherein said plurality of serially connected semiconductor gates of said delay circuit having first and second group of gates;   said first group of gates which is a set of semiconductor gates in an input side of said semiconductor gates, said first group of gates generating a reset pulse based on said pulse signal;   said second group of gates which is a set of semiconductor gates in an output side of said semiconductor gates, said second group of gates generating a set pulse based on said pulse signal;   a flip-flop which is set by said set pulse from said second group of gates and is reset by said reset pulse from said first group of gates;   an integrator which integrates an output signal of said flip-flop to produce an average voltage indicating a duty cycle of said output signal;   a first delay time control voltage generator which compares said average voltage from said integrator and a reference voltage indicating a delay time for said logic circuit and generates a first control voltage which is applied to said logic circuit and said delay circuit; and   a second delay time control voltage generator which receives said first control voltage from said first delay time control voltage generator and generates a second control voltage which is symmetrical to said first control voltage and is applied to said logic circuit and said delay circuit.   
     
     
       2. A delay time control circuit as defined in claim 1, wherein said reference voltage to said first delay time control voltage generator is given by a digital-analog converter which converts a digital signal indicating said delay time for said logic circuit into a corresponding analog reference voltage. 
     
     
       3. A delay time control circuit as defined in claim 1, therein each of said semiconductor gates in said delay circuit and said logic circuit is an inverter having a first control gate which is provided with said first control voltage from said first delay time control voltage generator and a second control gate which is provided with said second control voltage from said second delay time control voltage generator. 
     
     
       4. A delay time control circuit as defined in claim 1, wherein said delay circuit is formed in close proximity to said logic circuit in an integrated circuit. 
     
     
       5. A delay time control circuit as defined in claim 1, wherein said semiconductor gates in said delay circuit and said logic circuit are CMOS gates. 
     
     
       6. A delay time control circuit as defined in claim 1, wherein said integrator is a smoothing circuit formed of a series resistance and a parallel capacitance. 
     
     
       7. A delay time control circuit as defined in claim 1, wherein said first delay time control voltage generator is a differential amplifier having two symmetrical input terminals one of which is provided with said average voltage from said integrator and the other is provide with said reference voltage. 
     
     
       8. A delay time control circuit as defined in claim 1, wherein said second delay time control voltage generator comprising: a reference voltage generator which generates a second reference voltage which is an intermediate voltage of a higher source voltage and a lower source voltage to said logic circuit and said delay circuit;   a threshold voltage generator which generates an intermediate voltage of the first control voltage and said second control voltage; and   a second control voltage generator which compares said intermediate voltages from said reference voltage generator and said threshold voltage generator and generates said second control voltage which is proportional to a difference between said intermediate voltages.   
     
     
       9. A delay time control circuit as defined in claim 1, wherein said first control voltage is a negative voltage for said logic circuit and said delay circuit, and said second control voltage is a positive voltage for said logic circuit and said delay circuit. 
     
     
       10. A delay time control circuit as defined in claim 1, wherein said delay circuit, logic circuit, flip-flop, integrator, first and second delay time control voltage control voltage generators are formed in one integrated circuit. 
     
     
       11. A delay time control circuit for controlling delay times of a logic circuit which determines timings of test signals in a semiconductor test system, comprising: a delay circuit having a plurality of serially connected semiconductor gates which are the same type of semiconductor gates in said logic circuit;   a pulse signal supplied to said delay circuit;   wherein said plurality of serially connected semiconductor gates of said delay circuit having first and second group of gates;   said first group of gates which is a set of semiconductor gates in an input side of said semiconductor gates, said first group of gates generating a reset pulse based on said pulse signal;   said second group of gates which is a set of semiconductor gates in an output side of said semiconductor gates, said second group of gates generating a set pulse based on said pulse signal;   a flip-flop which is set by said set pulse from said second group of gates and is reset by said reset pulse from said first group of gates;   an integrator which integrates an output signal of said flip-flop to produce an average voltage indicating a duty cycle of said output signal; and   a delay time control voltage generator which compares said average voltage from said integrator and a reference voltage indicating a delay time for said logic circuit and generates a control voltage which is applied to said logic circuit and said delay circuit, said control voltage changes a rise and fall time of a logic signal in said logic circuit.   
     
     
       12. A delay time control circuit as defined in claim 11, wherein said reference voltage to said delay time control voltage generator is given by a digital-analog converter which converts a digital signal indicating said delay time for said logic circuit into a corresponding analog reference voltage. 
     
     
       13. A delay time control circuit as defined in claim 11, wherein each of said semiconductor gates in said delay circuit and said logic circuit is an inverter having a control gate which is provided with said control voltage from said delay time control voltage generator to control said rise and fall times by changing a time constant of said inverter.