Semiconductor chip scale package and method of producing such

Abstract

A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

What is claimed is: 
     
       1. A semiconductor chip scale package comprising: a semiconductor chip having signal leading bumps;   a printed circuit board (PCB) bonded to the lower surface of the chip and electrically connected to the chip, thus transmitting input and output signals to or from the chip;   a plurality of solder balls formed on the lower surface of said PCB and used as signal input and output terminals of the package;   an epoxy resin layer bonding said chip to the PCB; and   said PCB comprising a polymer resin substrate, a copper circuit pattern and a solder mask, said copper circuit pattern including a chip bump land and a solder ball land, said lands electrically connecting said signal leading bumps of the chip to said solder balls.   
     
     
       2. The package according to claim 1, wherein said PCB comprises: two or more polymer resin substrates and two or more copper circuit patterns alternately layered on each other;   a solder mask formed on the top surface of the PCB; and   said copper circuit patterns neighboring on each other and being electrically connected together through a via thus causing the solder balls to commonly have a power signal and/or a ground by connection of one of said signal leading bumps.   
     
     
       3. The package according to claim 1 or 2, wherein said package has an area of not larger than 120% of the size of said semiconductor chip. 
     
     
       4. The package according to claim 1 or 2, wherein said chip bump land and solder ball land are commonly formed on one copper circuit pattern in such as manner that: the chip bump land is defined on the copper circuit pattern on the bottom of a bump seating opening formed by said solder mask; and said solder ball land is defined on the copper circuit pattern on the bottom of a solder ball seating opening formed by partially removing the polymer resin from said substrate. 
     
     
       5. The package according to claim 4, further comprising an Ni coating layer formed on each of said lands and an Au coating layer formed on said Ni coating layer. 
     
     
       6. The package according to claim 5, wherein each of said Ni and Au coating layers has a thickness of higher than 0.3 μ. 
     
     
       7. The package according to claim 4, wherein said chip bump land is formed on the top surface of one end of the copper circuit pattern inside the bump seating opening and is located on a position spaced apart inward from the outside edge of the copper circuit pattern by a distance greater than 0.05 mm, while said solder ball land is formed on the bottom surface of the other end of said copper circuit pattern inside the solder ball seating opening. 
     
     
       8. The package according to claim 4, wherein said chip bump land is formed on the top surface of one end of the copper circuit pattern inside the bump seating opening and on an arcuate section of the top surface of said substrate exposed to the bump seating opening at a position around the end of the copper circuit pattern, with the distal end of said copper circuit pattern being spaced apart from the side wall of the bump seating opening by a distance greater than 0.05 mm, while said solder ball land is formed on the bottom surface of the other end of said copper circuit pattern inside the solder ball seating opening. 
     
     
       9. The package according to claim 1 or 2, wherein said signal leading bumps are made of Au, Sn/Pb solder or an alloy of Au and Sn/Pb solder. 
     
     
       10. A method for producing a semiconductor chip scale package, comprising the steps of: forming a copper circuit pattern on one side of a polymer resin substrate;   forming a bump seating opening by forming a solder mask on the one side of the substrate except for a position where a signal leading bump of a semiconductor chip is to be welded to the copper circuit pattern;   forming a solder ball seating opening on the opposite side of said substrate;   welding the bump of the chip into said bump seating opening;   filling a gap between the chip and the solder mask with epoxy resin prior to hardening said epoxy resin; and   welding a solder ball into said solder ball seating opening.   
     
     
       11. The method according to claim 10, wherein the step of forming a copper circuit pattern comprises the steps of: alternately arranging two or more polymer resin substrates and two or more copper circuit patterns on each other; and   electrically connecting said copper circuit patterns together through a via, thus causing a plurality of solder balls to commonly have a power signal and/or a ground by connection of said signal leading bump.   
     
     
       12. The method according to claim 10 or 11, wherein said package has an area of not larger than 120% of the size of said semiconductor chip. 
     
     
       13. The method according to claim 10 or 11, wherein said solder ball seating opening is formed through an etching or laser radiating process. 
     
     
       14. The method according to claim 10 or 11, wherein said solder ball seating opening is formed by punching said substrate prior to forming the copper circuit pattern. 
     
     
       15. The method according to claim 10 or 11, wherein an Ni coating layer is formed on the bottom of each of said seating openings and an Au coating layer is formed on said Ni coating layer, thus forming a chip bump land and a solder ball land during the steps of forming the seating openings. 
     
     
       16. The method according to claim 15, wherein each of said Ni and Au coating layers has a thickness of higher than 0.3 μ. 
     
     
       17. The method according to claim 15, wherein said chip bump land is formed on the top surface of one end of the copper circuit pattern inside the bump seating opening and is located on a position spaced apart inward from the outside edge of the copper circuit pattern by a distance greater than 0.05 mm, while said solder ball land is formed on the bottom surface of the other end of said copper circuit pattern inside the solder ball seating opening. 
     
     
       18. The package according to claim 15, wherein said chip bump land is formed on the top surface of one end of the copper circuit pattern inside the bump seating opening and on an arcuate section of the top surface of said substrate exposed to the bump seating opening at a position around the end of the copper circuit pattern, with the distal end of said copper circuit pattern being spaced apart from the side wall of the bump seating opening by a distance greater than 0.05 mm, while said solder ball land is formed on the bottom surface of the other end of said copper circuit pattern inside the solder ball seating opening.