EPROM manufacturing process having a floating gate with a large surface area

Abstract

The method for forming a "U" shaped floating gate 120a with high vertical projections 120c, begins by forming a dielectric layer 110 over the substrate 100. A photoresist layer 112 is then formed on the dielectric layer 110 and patterned to form a first opening 113. The first opening 113 exposes the dielectric layer 110. In an important step, a polymer layer 114 is formed over the photoresist layer 112 and on the vertical sidewalls of the first opening 113 thereby forming a second opening 115. The second opening 115 has a smaller width than that of the first opening 113. The dielectric layer 110 is anisotropically etched thru the second opening 115 thereby forming a third opening 116 in the dielectric layer 110. The photoresist layer 112 and the polymer layer 114 are now removed. The exposed substrate within the third opening 116 is thermally oxidized to form a tunnel oxide layer 118. A first polysilicon layer 120 is formed conformally on the resultant surface and in the third opening. The first polysilicon layer is chemically mechanically polished, thereby forming the U-shaped floating gate 120a in the third opening 116. An intergate dielectric layer 122 and a control gate 124A are then formed on the floating gate 120a to complete the EPROM.

What is claimed is: 
     
       1. A method of forming a floating gate in the fabrication of a semiconductor device and on a semiconductor substrate, comprising the steps of: a) forming a dielectric layer on said semiconductor substrate;   b) forming a photoresist layer on said dielectric layer, and patterning said photoresist layer, to form a first opening with vertical sidewalls through said photoresist layer, the first opening exposing said dielectric layer;   c) forming a polymer layer over said photoresist layer and on said vertical sidewalls of said photoresist in said first opening thereby forming a second opening smaller than said first opening;   d) anisotropically etching said polymer layer and said dielectric layer through said second opening and leaving remaining portions of said polymer layer thereby forming a third opening with vertical sidewalls in said dielectric layer and exposing a surface of said substrate;   e) removing said photoresist layer and said remaining portions of said polymer layer;   f) thermally oxidizing the exposed substrate surface thereby forming a tunnel oxide layer on said substrate surface;   g) forming a first polysilicon layer conformally on said dielectric layer and on said vertical sidewalls of said third opening in said dielectric layer and on said tunnel oxide layer;   h) chemical mechanical polishing said first polysilicon layer thereby removing a portion of said polysilicon layer over said dielectric layer and leaving a remaining portion inside the third opening; the remaining portion of said first polysilicon layer inside the third opening forming a floating gate on said tunnel oxide layer, said floating gate having a U-shape comprising a horizontal base and two vertical projections;   i) removing said dielectric layer;   j) forming an intergate dielectric layer conformally on said substrate and on said floating gate;   k) forming a second polysilicon layer conformally on said intergate dielectric layer;   l) patterning said second polysilicon layer and said intergate dielectric layer forming a control gate from said second polysilicon layer; and   m) forming spaced source and drain regions in said substrate adjacent to said control gate.   
     
     
       2. The method of claim 1 wherein said dielectric layer has a thickness in a range of between about 2500 and 3500 Å. 
     
     
       3. The method of claim 1 wherein the width of said first opening is between about 0.2 to 0.3 μm. 
     
     
       4. The method of claim 1 wherein said polymer layer has a thickness of between about 400 and 600 Å. 
     
     
       5. The method of claim 1 wherein said third opening has an open dimension of between about 0.2 and 0.3 μm. 
     
     
       6. The method of claim 1 wherein said first polysilicon layer has a thickness in a range of between about 500 and 1500 Å. 
     
     
       7. The method of claim 1 wherein said intergate dielectric layer has a thickness of between about 50 and 200 Å. 
     
     
       8. The method of claim 1 wherein said second polysilicon layer has a thickness of between about 1000 and 2000 Å. 
     
     
       9. The method of claim 1 wherein said vertical projections have a height of between about 2500 and 3500 Å. 
     
     
       10. A method of manufacturing an EPROM device having a floating gate on a semiconductor substrate, said method comprising the steps of: a) forming a dielectric layer on said semiconductor substrate; said dielectric layer having a thickness between about 2500 and 3500 Å;   b) forming a photoresist layer on said dielectric layer;   c) patterning said photoresist layer using a photolithographic exposing, developing, and etching process to form a first opening in said photoresist layer with vertical sidewalls, said first opening exposing said dielectric layer; said first opening having an open dimension between about 0.2 to 0.3 μm;   d) forming a polymer layer over said photoresist layer and on said vertical sidewalls of said first opening thereby forming a second opening smaller than said first opening; said polymer layer having a thickness of between about 400 and 600 Å;   e) anisotropically etching said polymer layer and said dielectric layer through said second opening and leaving remaining portions of said polymer layer thereby forming a third opening with vertical sidewalls in said dielectric layer and exposing a surface of said substrate;   f) removing said photoresist layer and said remaining portions of said polymer layer;   g) thermally oxidizing the exposed substrate surface forming a tunnel oxide layer;   h) forming a first polysilicon layer conformally on said dielectric layer and on said vertical sidewalls of said third opening and on said tunnel oxide layer; said first polysilicon layer having a thickness in a range of between about 500 and 1500 Å;   i) chemical mechanical polishing said first polysilicon layer thereby removing a portion of said polysilicon layer over said dielectric layer and leaving a remaining portion inside the third opening; the remaining portion of said first polysilicon layer inside the third opening forming a floating gate on said tunnel oxide layer, said floating gate having a U-shape comprised of a horizontal base and two vertical projections; said vertical projections having a height of between about 2500 and 3500 Å;   j) removing said dielectric layer;   k) forming an intergate dielectric layer conformally on said substrate and on said floating gate;   l) forming a second polysilicon layer conformally on said intergate dielectric layer; said second polysilicon layer having a thickness of between about 1000 and 2000 Å;   m) patterning said second polysilicon layer and said intergate dielectric layer to form a control gate from said second polysilicon layer; and   n) forming spaced source and drain regions in said substrate adjacent to said control gate thereby completing said EPROM device.