Etching method

Abstract

An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C 4 H 8 , CH 2 F 2 , and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C 4 H 8 , CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C 4 H 8 , CH 2 F 2 , CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

What is claimed is: 
     
       1. An etching method used in a high density plasma etching system to etch a silicon oxide dielectric layer for forming openings of different depth, comprising: performing a first stage of an etching process on the dielectric silicon oxide layer using a mixture of C 4  H 8 , CH 2  F 2 , and Ar as an etching gas source;   performing a second stage of the etching process on the dielectric layer using a mixture of C 4  H 8 , CO, and Ar as an etching gas source; and   performing a third stage of the etching process on the dielectric silicon oxide layer using a mixture of C 4  H 8 , CH 2  F 2 , CO, and Ar as an etching gas source.   
     
     
       2. The etching method of claim 1, wherein the first stage of the etching process is performed under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CH 2  F 2  of about 1 sccm to 50 sccm; and   a flow rate of Ar of about 1 sccm to 500 sccm.   
     
     
       3. The etching method of claim 2, wherein the first stage of the etching process is performed under conditions of: a pressure of about 4 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       4. The etching method of claim 1, wherein the second stage of the etching process is performed under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CO of about 1 sccm to 100 sccm; and   a flow rate of Ar of about 100 sccm to 500 sccm.   
     
     
       5. The etching method of claim 4, wherein the second stage of the etching process is performed under conditions of: a pressure of about 4 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       6. The etching method of claim 1, wherein the first stage of the etching process is performed under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CH 2  F 2  of about 1 sccm to 50 sccm;   a flow rate of CO of about 1 sccm to 100 sccm; and   a flow rate of Ar of about 1 sccm to 500 sccm.   
     
     
       7. The etching method of claim 6, wherein the third stage of the etching process is performed under conditions of: a pressure of about 10 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       8. An etching method performed on a silicon oxide dielectric layer in a high density plasma system, wherein the silicon oxide dielectric layer is formed to cover a source/drain region and a gate on a substrate and a polysilicon layer over the substrate, the etching method comprising: etching the silicon oxide dielectric layer with a mixture of C 4  H 8 , CH 2  F 2 , and Ar as an etching gas source to form a plurality of openings with a first depth using the polysilicon layer as an etching stop, so that the polysilicon layer is exposed by one of the openings, while two of the openings are aligned over the source/drain region and the gate;   deepening the openings to a second depth while the silicon oxide dielectric layer under a bottom of the openings are thicker than about 5000 Å, wherein the silicon oxide dielectric layer is further etched with a mixture of C 4  H 8 , CO and Ar as an etching gas source; and   further deepening the openings until the gate and the source/drain region is exposed while the silicon oxide dielectric layer under the bottom of the openings are thinner than about 5000 Å, wherein the silicon oxide dielectric layer is etched with a mixture of C 4  H 8 , CH 2  F 2 , CO and Ar as an etching gas source.   
     
     
       9. The etching method of claim 8, wherein the openings with the first depth are formed under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CH 2  F 2  of about 1 sccm to 50 sccm; and   a flow rate of Ar of about 1 sccm to 500 sccm.   
     
     
       10. The etching method of claim 9, wherein the openings with the first depth are formed under conditions of: a pressure of about 4 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       11. The etching method of claim 8, wherein the openings with the second depth are formed under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CO of about 1 sccm to 100 sccm; and   a flow rate of Ar of about 100 sccm to 500 sccm.   
     
     
       12. The etching method of claim 11, wherein the openings with the first depth are formed under conditions of: a pressure of about 4 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       13. The etching method of claim 8, wherein the openings are further deepened under conditions of: a flow rate of C 4  F 8  of about 10 sccm to 20 sccm;   a flow rate of CH 2  F 2  of about 1 sccm to 50 sccm;   a flow rate of CO of about 1 sccm to 100 sccm; and   a flow rate of Ar of about 1 sccm to 100 sccm.   
     
     
       14. The etching method of claim 13, wherein the openings are further deepened under conditions of: a pressure of about 10 mtorr to 100 mtorr;   a bias of about 1000 W to 2000 W;   a power of about 500 W to 3000 W;   a roof temperature of about 150° C. to 300° C.;   a ring temperature of about 150° C. to 400° C.; and   a chiller temperature of about -20° C. to 20° C.   
     
     
       15. The etching method according to claim 8, wherein the gate is covered by a cap layer which is removed while the openings are further deepened. 
     
     
       16. The etching method according to claim 8, wherein a byproduct is formed to cover the polysilicon layer while the openings are formed with the first depth to expose the polysilicon layer.