IGBT with reduced forward voltage drop and reduced switching loss

Abstract

The boundary between the P type silicon base and N + buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

What is claimed is:  
     
       1. An IGBT chip having an N +  silicon buffer layer atop a P type silicon body; the top of said P type body having a top surface with intentional lattice damage, and heavy metal lifetime killing atoms disposed in and being preferentially located in the intentionally damaged lattice. 
     
     
       2. The chip of claim  1  which includes a germanium enriched silicon layer disposed between said P type body and said N +  buffer layer. 
     
     
       3. The chip of claim  1  wherein said silicon body has an increased P +  concentration. 
     
     
       4. The chip of claim  2  wherein said silicon body has an increased P +  concentration. 
     
     
       5. The chip of claim  3  which includes a germanium enriched silicon layer disposed between said P type body and said N +  buffer layer. 
     
     
       6. An IGBT chip having an N +  buffer layer disposed above a P type body and a germanium enriched layer disposed between and in contact with said P type body and said N +  buffer layer; and heavy metal atoms disposed within and adjacent to said germanium enriched layer. 
     
     
       7. The IGBT chip of claim  6  wherein said body has an increased P +  concentration. 
     
     
       8. The IGBT chip of claim  6  wherein said germanium enriched layer consists of about 1% germanium and about 99% silicon. 
     
     
       9. The IGBT chip of claim  8  wherein said P type body has an increased P +  concentration. 
     
     
       10. In an IGBT chip having a silicon P type body having top and bottom surfaces, a collector contact layer fixed to said bottom surface of said P type body, an N +  silicon buffer layer disposed atop said P type silicon body, an epitaxially deposited N +  layer disposed atop said N +  buffer layer, at least one P type base region diffused into the top of said N +  layer, an N +  emitter region diffused into said P type base region to define a channel region, an MOS gate structure disposed above said channel region and an emitter contact disposed above and in contact with said emitter region; the improvement which comprises a region of intentional damage of the lattice of said P type body at its said top surface to define accurately located lifetime killing sites in said lattice. 
     
     
       11. The IGBT chip of claim  10  wherein said region of intentional damage includes a germanium enriched layer of silicon disposed between said P type body and said N +  buffer layer and heavy metal atoms positioned at and uniformly distributed over the damaged lattice region. 
     
     
       12. The IGBT chip of claim  11  wherein said germanium enriched layer consists of about 1% germanium and about 99% silicon. 
     
     
       13. The IGBT chip of claim  1  wherein said P type body has an increased P +  concentration. 
     
     
       14. The IGBT chip of claim  13  wherein said region of intentional damage includes a germanium enriched layer of silicon disposed between said P type body and said N +  buffer layer and heavy metal atoms positioned at and uniformly distributed over the damaged lattice region. 
     
     
       15. The IGBT chip of claim  14  wherein said germanium enriched layer consists of about 1% germanium and about 99% silicon.