Method for forming a transistor with reduced source/drain series resistance

Abstract

A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer. Finally, the epi-silicon layer is treated with a salicidation process to form a salicide layer.

What is claimed is:  
     
       1. A method for manufacturing a transistor in integrated circuits, comprising: 
       providing a substrate;  
       forming an insulating layer on said substrate;  
       forming a conductor layer on said insulating layer;  
       forming a patterned photoresist layer on said conductor layer;  
       using said patterned photoresist layer as a mask to etch said conductor layer, said conductor layer having a sidewall;  
       removing said patterned photoresist layer;  
       forming a liner layer on said sidewall of said conductor layer;  
       introducing first ions to form a lightly doped drain region on and in said substrate by using said liner layer and the etched conductor layer as a mask;  
       forming a spacer on said liner layer;  
       introducing second ions into said lightly doped drain region to form a source/drain region by using said spacer, said liner layer and said etched conductor layer as a mask;  
       removing said spacer;  
       forming an epi-silicon layer on said lightly doped drain region, said source/drain region and top surface of said conductor layer; and  
       treating said epi-silicon layer with a salicidation process to form a salicide layer.  
     
     
       2. The method according to claim  1 , wherein said substrate comprises silicon. 
     
     
       3. The method according to claim  1 , wherein said insulating layer comprises a gate oxide layer. 
     
     
       4. The method according to claim  3 , wherein said gate oxide layer is formed by thermal oxidation process. 
     
     
       5. The method according to claim  1 , wherein said conductor layer comprises one of the following: poly-silicon, silicide and metal. 
     
     
       6. The method according to claim  1 , wherein said conductor layer is formed by deposition process. 
     
     
       7. The method according to claim  1 , wherein said liner layer is formed by deposition and etch back processes. 
     
     
       8. The method according to claim  1 , wherein said liner layer comprises silicon nitride. 
     
     
       9. The method according to claim  1 , wherein said liner layer has the thickness of about 100 to 300 angstroms. 
     
     
       10. The method according to claim  1 , wherein said lightly doped drain region is formed by ion implantation process. 
     
     
       11. The method according to claim  1 , wherein said spacer is formed by deposition and etch back processes. 
     
     
       12. The method according to claim  1 , wherein said spacer comprises oxide. 
     
     
       13. The method according to claim  1 , wherein said source/drain region is formed by ion implantation process. 
     
     
       14. The method according to claim  1 , wherein said spacer is removed by striping process. 
     
     
       15. The method according to claim  1 , wherein said spacer is removed by etch process. 
     
     
       16. The method according to claim  1 , wherein said epi-silicon layer comprises selective epi-silicon. 
     
     
       17. The method according to claim  1 , wherein said epi-silicon layer is formed by deposition process. 
     
     
       18. The method according to claim  1 , wherein said epi-silicon layer has the thickness of about 300 to 1000 angstroms. 
     
     
       19. The method according to claim  1 , wherein said salicidation process comprises: 
       depositing a metal on said epi-silicon layer; and  
       diffusing said metal into said epi-silicon layer by a thermal process.  
     
     
       20. The method according to claim  19 , wherein said metal comprises one of the following: Ti and Co.