Method of fabricating concave capacitor including adhesion spacer

Abstract

In accordance with the present invention, a method of fabricating a concave capacitor is provided. The concave capacitor of the present invention includes an adhesion spacer is formed between a concave pattern comprising an interlayer dielectric film and a lower electrode is provided. In the concave capacitor fabricating method, an interlayer dielectric film is formal semiconductor substrate. A concave pattern having a storage node e exposing part of the upper surface of the semiconductor substrate is form by patterning the interlayer dielectric film. An adhesion spacer is formed on t sidewall of the concave pattern exposed by the storage node hole. A lower electrode to cover the adhesion spacer and the upper surface of the semiconductor substrate exposed by the storage node hole is formed in the storage node hole

What is claimed is:  
     
       1. A method of fabricating a concave capacitor for a semiconductor memory device, comprising: 
       forming an interlayer dielectric film on a semiconductor substrate;  
       forming a concave pattern having a storage node hole exposing a portion of an upper surface of the semiconductor substrate, by patterning the interlayer dielectric film;  
       forming an adhesion spacer only on a sidewall of the concave pattern exposed by the storage node hole; and  
       forming a lower electrode to cover the adhesion spacer and the upper surface of the semiconductor substrate exposed by the storage node hole, in the storage node hole.  
     
     
       2. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  1 , wherein in forming the interlayer dielectric film, the semiconductor substrate includes a contact having one end connected to an active region of the semiconductor substrate and the other end exposed on the upper surface of the semiconductor substrate, and in forming the concave pattern, the other end of the contact is exposed by the storage node hole. 
     
     
       3. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  2 , wherein the other end of the contact is formed of a material selected from the group consisting of TiN, TiAIN, TiSiN, TaN, TaSiN and TaAlN. 
     
     
       4. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  1 , wherein in forming the interlayer dielectric film, the interlayer dielectric film has a structure in which an etch stop layer, an oxide layer, and an anti-reflection layer are sequentially stacked. 
     
     
       5. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  4 , wherein the etch stop layer is formed of SiN. 
     
     
       6. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  1 , wherein forming the adhesion spacer comprises: 
       forming an adhesion layer for covering the semiconductor substrate exposed by the storage node hole, and the sidewall and upper surface of the concave pattern; and  
       etching back the adhesion layer so that the adhesion spacer can remain only on the sidewall of the concave pattern.  
     
     
       7. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  6 , wherein the adhesion layer is formed by depositing at least one material selected from the group consisting of Ti, TiN, TiSiN, TiAIN, TiO 2 , Ta, Ta 2 O 5 , TaN, TaAIN, TaSiN, AI 2 O 3 , W,WN, Co, and CoSi. 
     
     
       8. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  7 , wherein the adhesion layer is formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a metal-organic deposition (MOD) method, a sol-gel method, or an atomic layer deposition (ALD) method. 
     
     
       9. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  1 , wherein forming the lower electrode comprises: 
       forming a first conductive layer to cover an upper surface of the contact and the adhesion spacer which are exposed in the storage node hole, and an upper surface of the concave pattern;  
       forming a sacrificial layer having a thickness that can completely fill the storage node hole, on the first conductive layer;  
       dividing the first conductive layer into a plurality of lower electrodes by removing the first conductive layer and sacrificial layer on the concave pattern until the upper surface of the concave pattern is exposed; and  
       removing residual portion of the sacrificial layer.  
     
     
       10. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  9 , wherein the first conductive layer is formed of a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, and an oxide having a perovskite structure. 
     
     
       11. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  9 , wherein the sacrificial layer is a photoresist layer or an oxide layer. 
     
     
       12. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  9 , wherein in dividing the first conductive layer, the first conductive layer and sacrificial layer on the concave pattern are removed by an etch-back method or a chemical mechanical polishing (CMP) method. 
     
     
       13. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  11 , wherein the sacrificial layer is a photoresist layer, and the residual portion of the sacrificial layer is removed by ashing in the removal of the residual part of the sacrificial layer. 
     
     
       14. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  11 , wherein the sacrificial layer is an oxide layer, and the residual portion of the sacrificial layer is wet-etched out in the removal of the residual portion of the sacrificial layer. 
     
     
       15. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  1 , after forming the lower electrode, further comprises: 
       forming a dielectric layer on the lower electrode; and  
       forming a second conductive layer to form an upper electrode, on the dielectric layer.  
     
     
       16. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  15 , wherein the dielectric layer is formed of at least one material selected from the group consisting of Ta 2 O 5 , AI 2 O 3 , SiO 2 , SrTiO 3 , BaTiO 3 , (Ba,Sr)TiO 3 , PbTiO 3 , (Pb,Zr)TiO 3 , Pb(La,Zr)TiO 3 , Sr 2 Bi 2 NbO 9 , Sr 2 Bi 2 TaO 9 , LiNbO 3 , and Pb(Mg,Nb)O 3 . 
     
     
       17. The method of fabricating a concave capacitor for a semiconductor memory device as claimed in claim  15 , wherein the second conductive layer is formed of a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, TiN, and an oxide having a perovskite structure.